1998 |
10 | | S. Grout,
G. Ledenbach,
R. G. Bushroe,
P. Fisher,
D. Cottrell,
D. Mallis,
S. DasGupta,
J. Morrell,
J. Sayah,
R. Gupta,
P. T. Patel,
P. Adams:
Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis.
ASP-DAC 1998: 257-260 |
9 | EE | S. Grout,
G. Ledenbach,
R. G. Bushroe,
P. Fisher,
D. Cottrell,
D. Mallis,
S. DasGupta,
J. Morrell,
Amrich Chokhavtia:
CHDStd - application support for reusable hierarchical interconnect timing views.
ISPD 1998: 75-79 |
8 | EE | S. DasGupta:
Panel: Given that SEMATECH is levelling the semiconductor technology playing field, will corporate CAD (in particular, PD) tools continue to serve as enablers/differentiators of technology in the future? (panel).
ISPD 1998: 86 |
1997 |
7 | EE | R. G. Bushroe,
S. DasGupta,
A. Dengi,
P. Fisher,
S. Grout,
G. Ledenbach,
N. S. Nagaraj,
R. Steele:
Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century.
ISPD 1997: 212-217 |
1990 |
6 | EE | S. DasGupta,
M. Hohenberger,
Len Trejo,
T. Kaylani:
Effect of data compression of ERP sign preprocessed by FWT algorithm upon a neural network classifier.
Annual Simulation Symposium 1990: 63-71 |
5 | EE | F. Kampf,
P. Koch,
K. Roy,
M. Sullivan,
Z. Delalic,
S. DasGupta:
Optimization of a digital neuron design.
Annual Simulation Symposium 1990: 73-80 |
1989 |
4 | EE | M. R. Brown,
S. DasGupta:
Design of a general purpose meta-assembler for parallel processor environment in ISPS.
Annual Simulation Symposium 1989: 105-117 |
3 | | S. DasGupta,
Kalapi Roy:
Description Language for a Neural Network Architecture.
IAS 1989: 294-304 |
1987 |
2 | EE | S. DasGupta,
H. Chang:
Simulation of a computer with variable hardware and variable instruction set.
Annual Simulation Symposium 1987: 1-12 |
1986 |
1 | EE | J. M. Hancock,
S. DasGupta:
Tutorial on parallel processing for design automation applications (tutorial session).
DAC 1986: 69-77 |