1998 |
3 | | S. Grout,
G. Ledenbach,
R. G. Bushroe,
P. Fisher,
D. Cottrell,
D. Mallis,
S. DasGupta,
J. Morrell,
J. Sayah,
R. Gupta,
P. T. Patel,
P. Adams:
Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis.
ASP-DAC 1998: 257-260 |
2 | EE | S. Grout,
G. Ledenbach,
R. G. Bushroe,
P. Fisher,
D. Cottrell,
D. Mallis,
S. DasGupta,
J. Morrell,
Amrich Chokhavtia:
CHDStd - application support for reusable hierarchical interconnect timing views.
ISPD 1998: 75-79 |
1997 |
1 | EE | R. G. Bushroe,
S. DasGupta,
A. Dengi,
P. Fisher,
S. Grout,
G. Ledenbach,
N. S. Nagaraj,
R. Steele:
Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century.
ISPD 1997: 212-217 |