| 2008 |
|---|
| 9 | EE | Shin'ichi Miura,
Takayuki Okamoto,
Taisuke Boku,
Toshihiro Hanawa,
Mitsuhisa Sato:
RI2N: High-bandwidth and fault-tolerant network with multi-link Ethernet for PC clusters.
CLUSTER 2008: 274-279 |
| 8 | EE | Shin'ichi Miura,
Taisuke Boku,
Takayuki Okamoto,
Toshihiro Hanawa:
A dynamic routing control system for high-performance PC cluster with multi-path Ethernet connection.
IPDPS 2008: 1-8 |
| 2005 |
|---|
| 7 | | Toshihiro Hanawa,
Toshiya Minai,
Yasuki Tanabe,
Hideharu Amano:
Implementation of ISIS-SimpleScalar.
PDPTA 2005: 117-123 |
| 6 | EE | Takashi Midorikawa,
Daisuke Shiraishi,
Masayoshi Shigeno,
Yasuki Tanabe,
Toshihiro Hanawa,
Hideharu Amano:
The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism).
Parallel Computing 31(3-4): 352-370 (2005) |
| 2003 |
|---|
| 5 | | Yasuki Tanabe,
Takashi Midorikawa,
Daisuke Shiraishi,
Masayoshi Shigeno,
Toshihiro Hanawa,
Hideharu Amano:
Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism.
PDPTA 2003: 1148-1154 |
| 1999 |
|---|
| 4 | | Junji Yamamoto,
Takashi Fujiwara,
T. Komeda,
Takayuki Kamei,
Toshihiro Hanawa,
Hideharu Amano:
Performance evaluation of SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture.
Parallel Computing 25(9): 1081-1103 (1999) |
| 1998 |
|---|
| 3 | | Takashi Midorikawa,
Takayuki Kamei,
Toshihiro Hanawa,
Hideharu Amano:
The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip.
ASP-DAC 1998: 337-338 |
| 1997 |
|---|
| 2 | | Akira Funahashi,
Toshihiro Hanawa,
Hideharu Amano,
Tomohiro Kudoh:
Adaptive Routing on the Recursive Diagonal Torus.
ISHPC 1997: 171-182 |
| 1994 |
|---|
| 1 | | Toshihiro Hanawa,
Hideharu Amano,
Yoshifumi Fujikawa:
Multistage Interconnection Networks with Multiple Outlets.
ICPP (1) 1994: 1-8 |
