| 2001 |
|---|
| 9 | EE | Qinwei Xu,
Pinaki Mazumder,
Mayukh Bhattacharya:
Modeling of Nonuniform Interconnects by Using Differential Quadrature Method.
VLSI Design 2001: 327-332 |
| 8 | EE | Mayukh Bhattacharya,
Pinaki Mazumder,
Ronald J. Lomax:
Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates.
VLSI Design 2001: 470-474 |
| 7 | EE | Kanad Chakraborty,
Shriram Kulkarni,
Mayukh Bhattacharya,
Pinaki Mazumder,
Anurag Gupta:
A physical design tool for built-in self-repairable RAMs.
IEEE Trans. VLSI Syst. 9(2): 352-364 (2001) |
| 6 | EE | Mayukh Bhattacharya,
Pinaki Mazumder:
Augmentation of SPICE for simulation of circuits containingresonant tunneling diodes.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 39-50 (2001) |
| 2000 |
|---|
| 5 | EE | Alejandro F. González,
Mayukh Bhattacharya,
Shriram Kulkarni,
Pinaki Mazumder:
Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices.
ISMVL 2000: 323- |
| 4 | EE | Mayukh Bhattacharya,
Pinaki Mazumder:
Convergence Issues in Resonant Tunneling Diode Circuit Simulation.
VLSI Design 2000: 499- |
| 1999 |
|---|
| 3 | EE | Kanad Chakraborty,
Anurag Gupta,
Mayukh Bhattacharya,
Shriram Kulkarni,
Pinaki Mazumder:
A Physical Design Tool for Built-in Self-Repairable Static RAMs.
DATE 1999: 714- |
| 1998 |
|---|
| 2 | EE | Mayukh Bhattacharya,
Pinaki Mazumder:
Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes.
Great Lakes Symposium on VLSI 1998: 65-70 |
| 1 | EE | Pinaki Mazumder,
Shriram Kulkarni,
Mayukh Bhattacharya,
Alejandro F. González:
Circuit Design using Resonant Tunneling Diodes.
VLSI Design 1998: 501-506 |
