| |
| 2001 | ||
|---|---|---|
| 2 | EE | Sitaram Yadavalli, Sandip Kundu: On Fault-Simulation Through Embedded Memories On Large Industrial Designs. VLSI Design 2001: 117-121 |
| 1998 | ||
| 1 | Sitaram Yadavalli, Sanjay Sengupta: Impact and Cost of Modeling Memories for ATPG for Partial Scan Designs. VLSI Design 1998: 274-278 | |
| 1 | Sandip Kundu | [2] |
| 2 | Sanjay Sengupta | [1] |