Wei Hwang

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27EEPo-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang: "Green" micro-architecture and circuit co-design for ternary content addressable memory. ISCAS 2008: 3322-3325
26EELi-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang: A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. ISCAS 2008: 3342-3345
25EEPo-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang: Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. NOCS 2008: 77-83
24EEMu-Tien Chang, Po-Tsang Huang, Wei Hwang: A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. SoCC 2008: 175-178
23EEWei-Chih Hsieh, Wei Hwang: In-situ self-aware adaptive power control system with multi-mode power gating network. SoCC 2008: 215-218
22EEHao-I Yang, Ssu-Yun Lai, Wei Hwang: Low-power floating bitline 8-T SRAM design with write assistant circuits. SoCC 2008: 239-242
21EEMing-Hung Chang, Li-Pu Chuang, I-Ming Chang, Wei Hwang: A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration. SoCC 2008: 97-100
20EEMing-Hung Chang, Zong-Xi Yang, Wei Hwang: A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation. ISCAS 2007: 1137-1140
19EEWei-Chih Hsieh, Wei Hwang: Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage Control. ISCAS 2007: 1637-1640
18EEPo-Tsang Huang, Wei-Keng Chang, Wei Hwang: Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. APCCAS 2006: 1301-1304
17EEChi-Chen Lai, Wei Hwang: A Low-Power Reconfigurable Mixed-Radix FFT/IFFT Processor. APCCAS 2006: 1931-1934
16EEJen-Wei Yang, Po-Tsang Huang, Wei Hwang: On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. APCCAS 2006: 666-669
15EEPo-Tsang Huang, Wei Hwang: 2-level FIFO architecture design for switch fabrics in network-on-chip. ISCAS 2006
14EETzu-Chiang Chao, Wei Hwang: A 1.7mW all digital phase-locked loop with new gain generator and low power DCO. ISCAS 2006
13EEChung-Hsien Hua, Chi-Wei Peng, Wei Hwang: A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM. ISCAS 2006
12EEChung-Hsien Hua, Wei Hwang, Chih-Kai Chen: Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits. ISCAS (1) 2005: 444-447
11EESangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang: Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization. VLSI Signal Processing 38(2): 101-113 (2004)
10EEStephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban: Low-power circuits and technology for wireless digital systems. IBM Journal of Research and Development 47(2-3): 283-298 (2003)
9EERajiv V. Joshi, Wei Hwang, Ching-Te Chuang: SOI for asynchronous dynamic circuits. ACM Great Lakes Symposium on VLSI 2001: 37-42
8EEW. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi: Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. ISLPED 2001: 263-266
7EERajiv V. Joshi, Wei Hwang, Andreas Kuehlmann: Design Of Provably Correct Storage Arrays. VLSI Design 2001: 196-
6EEGeorge Gristede, Wei Hwang: A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications. ACM Great Lakes Symposium on VLSI 2000: 101-106
5EERajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang: "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). ISLPED 2000: 203-206
4EERajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang: A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. VLSI Design 2000: 44-49
3EERajiv V. Joshi, Wei Hwang: Design Considerations and Implementation of a High Performance Dynamic Register File. VLSI Design 1999: 526-531
2 W. K. Luk, Y. Katayama, Wei Hwang, Matthew R. Wordeman, T. Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi: Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD 1997: 279-285
1 Wei Hwang, Rajiv V. Joshi, Walter H. Henkels: A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. ICCD 1997: 712-717

Coauthor Index

1Azeez J. Bhavnagarwala [10]
2I-Ming Chang [21]
3Ming-Hung Chang [20] [21] [26]
4Mu-Tien Chang [24]
5Shu-Wei Chang [27]
6Wei-Keng Chang [18]
7Tzu-Chiang Chao [14]
8Chih-Kai Chen [12]
9W. Chen [8]
10Kenneth Chin [10]
11Shu-Shin Chin [11]
12Ching-Te Chuang [4] [5] [9]
13Li-Pu Chuang [21] [26]
14B. El-Kareh [2]
15Wei-Li Fang [25]
16George Gristede [6] [8] [10]
17Anne-Marie Haen [10]
18Walter H. Henkels [1]
19Sangjin Hong [11]
20Wei-Chih Hsieh [19] [23]
21Chung-Hsien Hua [12] [13]
22Po-Tsang Huang [15] [16] [18] [24] [25] [26] [27]
23Rajiv V. Joshi [1] [2] [3] [4] [5] [7] [8] [9]
24Chih-Hao Kan [26]
25Y. Katayama [2]
26Mark B. Ketchen [10]
27Suhwan Kim [10] [11]
28T. Kirihata [2]
29Daniel R. Knebel [10]
30Stephen V. Kosonocky [8] [10]
31Prabhakar Kudva [8]
32Andreas Kuehlmann [7]
33Chi-Chen Lai [17]
34Ssu-Yun Lai [22]
35Wen-Yen Liu [27]
36W. K. Luk [2]
37Seiji Munetoh [2]
38Chi-Wei Peng [13]
39Akashi Satoh [2]
40Ghavam V. Shahidi [4]
41Yin-Ling Wang [25]
42Kevin W. Warren [10]
43S. C. Wilson [4] [5]
44H. Wong [2]
45Matthew R. Wordeman [2]
46P. Xiao [2]
47Hao-I Yang [22]
48Jen-Wei Yang [16]
49Zong-Xi Yang [20]
50Victor V. Zyuban [10]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)