2008 |
27 | EE | Po-Tsang Huang,
Shu-Wei Chang,
Wen-Yen Liu,
Wei Hwang:
"Green" micro-architecture and circuit co-design for ternary content addressable memory.
ISCAS 2008: 3322-3325 |
26 | EE | Li-Pu Chuang,
Ming-Hung Chang,
Po-Tsang Huang,
Chih-Hao Kan,
Wei Hwang:
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop.
ISCAS 2008: 3342-3345 |
25 | EE | Po-Tsang Huang,
Wei-Li Fang,
Yin-Ling Wang,
Wei Hwang:
Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip.
NOCS 2008: 77-83 |
24 | EE | Mu-Tien Chang,
Po-Tsang Huang,
Wei Hwang:
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control.
SoCC 2008: 175-178 |
23 | EE | Wei-Chih Hsieh,
Wei Hwang:
In-situ self-aware adaptive power control system with multi-mode power gating network.
SoCC 2008: 215-218 |
22 | EE | Hao-I Yang,
Ssu-Yun Lai,
Wei Hwang:
Low-power floating bitline 8-T SRAM design with write assistant circuits.
SoCC 2008: 239-242 |
21 | EE | Ming-Hung Chang,
Li-Pu Chuang,
I-Ming Chang,
Wei Hwang:
A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration.
SoCC 2008: 97-100 |
2007 |
20 | EE | Ming-Hung Chang,
Zong-Xi Yang,
Wei Hwang:
A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation.
ISCAS 2007: 1137-1140 |
19 | EE | Wei-Chih Hsieh,
Wei Hwang:
Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage Control.
ISCAS 2007: 1637-1640 |
2006 |
18 | EE | Po-Tsang Huang,
Wei-Keng Chang,
Wei Hwang:
Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory.
APCCAS 2006: 1301-1304 |
17 | EE | Chi-Chen Lai,
Wei Hwang:
A Low-Power Reconfigurable Mixed-Radix FFT/IFFT Processor.
APCCAS 2006: 1931-1934 |
16 | EE | Jen-Wei Yang,
Po-Tsang Huang,
Wei Hwang:
On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology.
APCCAS 2006: 666-669 |
15 | EE | Po-Tsang Huang,
Wei Hwang:
2-level FIFO architecture design for switch fabrics in network-on-chip.
ISCAS 2006 |
14 | EE | Tzu-Chiang Chao,
Wei Hwang:
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO.
ISCAS 2006 |
13 | EE | Chung-Hsien Hua,
Chi-Wei Peng,
Wei Hwang:
A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM.
ISCAS 2006 |
2005 |
12 | EE | Chung-Hsien Hua,
Wei Hwang,
Chih-Kai Chen:
Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits.
ISCAS (1) 2005: 444-447 |
2004 |
11 | EE | Sangjin Hong,
Shu-Shin Chin,
Suhwan Kim,
Wei Hwang:
Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization.
VLSI Signal Processing 38(2): 101-113 (2004) |
2003 |
10 | EE | Stephen V. Kosonocky,
Azeez J. Bhavnagarwala,
Kenneth Chin,
George Gristede,
Anne-Marie Haen,
Wei Hwang,
Mark B. Ketchen,
Suhwan Kim,
Daniel R. Knebel,
Kevin W. Warren,
Victor V. Zyuban:
Low-power circuits and technology for wireless digital systems.
IBM Journal of Research and Development 47(2-3): 283-298 (2003) |
2001 |
9 | EE | Rajiv V. Joshi,
Wei Hwang,
Ching-Te Chuang:
SOI for asynchronous dynamic circuits.
ACM Great Lakes Symposium on VLSI 2001: 37-42 |
8 | EE | W. Chen,
Wei Hwang,
Prabhakar Kudva,
George Gristede,
Stephen V. Kosonocky,
Rajiv V. Joshi:
Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design.
ISLPED 2001: 263-266 |
7 | EE | Rajiv V. Joshi,
Wei Hwang,
Andreas Kuehlmann:
Design Of Provably Correct Storage Arrays.
VLSI Design 2001: 196- |
2000 |
6 | EE | George Gristede,
Wei Hwang:
A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications.
ACM Great Lakes Symposium on VLSI 2000: 101-106 |
5 | EE | Rajiv V. Joshi,
Wei Hwang,
S. C. Wilson,
Ching-Te Chuang:
"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session).
ISLPED 2000: 203-206 |
4 | EE | Rajiv V. Joshi,
Wei Hwang,
S. C. Wilson,
Ghavam V. Shahidi,
Ching-Te Chuang:
A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology.
VLSI Design 2000: 44-49 |
1999 |
3 | EE | Rajiv V. Joshi,
Wei Hwang:
Design Considerations and Implementation of a High Performance Dynamic Register File.
VLSI Design 1999: 526-531 |
1997 |
2 | | W. K. Luk,
Y. Katayama,
Wei Hwang,
Matthew R. Wordeman,
T. Kirihata,
Akashi Satoh,
Seiji Munetoh,
H. Wong,
B. El-Kareh,
P. Xiao,
Rajiv V. Joshi:
Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip.
ICCD 1997: 279-285 |
1 | | Wei Hwang,
Rajiv V. Joshi,
Walter H. Henkels:
A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit.
ICCD 1997: 712-717 |