2008 |
22 | EE | José A. Joao,
Onur Mutlu,
Hyesoon Kim,
Rishi Agarwal,
Yale N. Patt:
Improving the performance of object-oriented languages with dynamic predication of indirect jumps.
ASPLOS 2008: 80-90 |
21 | EE | Chang Joo Lee,
Hyesoon Kim,
Onur Mutlu,
Yale N. Patt:
Performance-aware speculation control using wrong path usefulness prediction.
HPCA 2008: 39-49 |
20 | EE | Nagesh B. Lakshminarayana,
Hyesoon Kim:
Understanding performance, power and energy behavior in asymmetric multiprocessors.
ICCD 2008: 471-477 |
2007 |
19 | EE | Hyesoon Kim,
José A. Joao,
Onur Mutlu,
Yale N. Patt:
Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors.
CGO 2007: 367-378 |
18 | EE | Santhosh Srinath,
Onur Mutlu,
Hyesoon Kim,
Yale N. Patt:
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers.
HPCA 2007: 63-74 |
17 | EE | Hyesoon Kim,
José A. Joao,
Onur Mutlu,
Chang Joo Lee,
Yale N. Patt,
Robert Cohn:
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization.
ISCA 2007: 424-435 |
16 | EE | José A. Joao,
Onur Mutlu,
Hyesoon Kim,
Yale N. Patt:
Dynamic Predication of Indirect Jumps.
Computer Architecture Letters 6(2): 25-28 (2007) |
15 | EE | Hyesoon Kim,
José A. Joao,
Onur Mutlu,
Yale N. Patt:
Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication.
IEEE Micro 27(1): 94-104 (2007) |
2006 |
14 | EE | Hyesoon Kim,
M. Aater Suleman,
Onur Mutlu,
Yale N. Patt:
2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set.
CGO 2006: 159-172 |
13 | EE | Hyesoon Kim,
José A. Joao,
Onur Mutlu,
Yale N. Patt:
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths.
MICRO 2006: 53-64 |
12 | EE | Onur Mutlu,
Hyesoon Kim,
Yale N. Patt:
Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance.
IEEE Micro 26(1): 10-20 (2006) |
11 | EE | Hyesoon Kim,
Onur Mutlu,
Yale N. Patt,
Jared Stark:
Wish Branches: Enabling Adaptive and Aggressive Predicated Execution.
IEEE Micro 26(1): 48-58 (2006) |
10 | EE | Onur Mutlu,
Hyesoon Kim,
Yale N. Patt:
Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses.
IEEE Trans. Computers 55(12): 1491-1508 (2006) |
2005 |
9 | EE | Onur Mutlu,
Hyesoon Kim,
Yale N. Patt:
Techniques for Efficient Processing in Runahead Execution Engines.
ISCA 2005: 370-381 |
8 | EE | Onur Mutlu,
Hyesoon Kim,
Yale N. Patt:
Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns.
MICRO 2005: 233-244 |
7 | EE | Hyesoon Kim,
Onur Mutlu,
Jared Stark,
Yale N. Patt:
Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution.
MICRO 2005: 43-54 |
6 | EE | Onur Mutlu,
Hyesoon Kim,
Jared Stark,
Yale N. Patt:
On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor.
Computer Architecture Letters 4(1): 2 (2005) |
5 | EE | Onur Mutlu,
Hyesoon Kim,
David N. Armstrong,
Yale N. Patt:
An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors.
IEEE Trans. Computers 54(12): 1556-1571 (2005) |
4 | EE | Onur Mutlu,
Hyesoon Kim,
David N. Armstrong,
Yale N. Patt:
Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References.
International Journal of Parallel Programming 33(5): 529-559 (2005) |
2004 |
3 | EE | David N. Armstrong,
Hyesoon Kim,
Onur Mutlu,
Yale N. Patt:
Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery.
MICRO 2004: 119-128 |
2 | EE | Onur Mutlu,
Hyesoon Kim,
David N. Armstrong,
Yale N. Patt:
Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance.
SBAC-PAD 2004: 2-9 |
1 | EE | Onur Mutlu,
Hyesoon Kim,
David N. Armstrong,
Yale N. Patt:
Understanding the effects of wrong-path memory references on processor performance.
WMPI 2004: 56-64 |