2009 |
25 | EE | Dawei Wang,
Sikun Li,
Yong Dou:
Loop Kernel Pipelining Mapping onto Coarse-Grained Reconfigurable Architecture for Data-Intensive Applications.
JSW 4(1): 81-89 (2009) |
2008 |
24 | EE | Jie Zhou,
Yong Dou,
Yuanwu Lei,
Yazhuo Dong:
Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.
ARC 2008: 254-259 |
23 | EE | Fei Xia,
Yong Dou,
Jinbo Xu:
Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension.
ARC 2008: 39-50 |
22 | EE | Dawei Wang,
Sikun Li,
Yong Dou:
Collaborative hardware/software partition of coarse-grained reconfigurable system using evolutionary ant colony optimization.
ASP-DAC 2008: 679-684 |
21 | | Fei Xia,
Yong Dou,
Jiaqing Xu:
Fine-Grained Parallel Zuker Algorithm Accelerator with Storage Optimization on FPGA.
BIOCOMP 2008: 538-544 |
20 | EE | Fei Xia,
Yong Dou,
Jiaqing Xu:
Families of FPGA-Based Accelerators for BLAST Algorithm with Multi-seeds Detection and Parallel Extension.
BIRD 2008: 43-57 |
19 | EE | Jie Zhou,
Yong Dou,
Yuanwu Lei,
Jinbo Xu,
Yazhuo Dong:
Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.
HPCC 2008: 182-189 |
18 | EE | Yong Dou,
Fei Xia,
Xingming Zhou,
Xuejun Yang:
Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGA.
ICCD 2008: 240-247 |
17 | EE | Yong Dou,
Lin Deng,
Jinhui Xu,
Yi Zheng:
DMA Performance Analysis and Multi-core Memory Optimization for SWIM Benchmark on the Cell Processor.
ISPA 2008: 170-179 |
2007 |
16 | EE | Fei Xia,
Yong Dou:
Reducing Storage Requirements in Accelerating Algorithm of Global BioSequence Alignment on FPGA.
APPT 2007: 90-99 |
15 | EE | Yazhuo Dong,
Yong Dou,
Jie Zhou:
Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware.
ARC 2007: 110-121 |
14 | EE | Yong Dou,
Jinhui Xu,
Guiming Wu:
The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining.
ARC 2007: 155-166 |
13 | EE | Xiaodong Yang,
Shengmei Mou,
Yong Dou:
FPGA-Accelerated Molecular Dynamics Simulations: An Overview.
ARC 2007: 293-301 |
12 | EE | Yong Dou,
Jie Zhou,
Yuanwu Lei,
Xingming Zhou:
FPGA SAR Processor with Window Memory Accesses.
ASAP 2007: 95-100 |
11 | EE | Yazhuo Dong,
Yong Dou:
A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications.
ASP-DAC 2007: 523-528 |
10 | EE | Yong Dou,
Jinbo Xu:
FPGA-Accelerated Active Shape Model for Real-Time People Tracking.
Asia-Pacific Computer Systems Architecture Conference 2007: 268-279 |
9 | EE | Sikun Li,
Dawei Wang,
Tun Li,
Yong Dou:
Distributed Collaborative Partition Method of Reconfigurable SoC Using Ant Colony Optimization.
CSCWD 2007: 133-138 |
8 | EE | Jinbo Xu,
Yong Dou,
Junfeng Li,
Xingming Zhou,
Qiang Dou:
FPGA Accelerating Algorithms of Active Shape Model in People Tracking Applications.
DSD 2007: 432-435 |
7 | EE | Bao-Feng Li,
Yong Dou:
FIDP: A Novel Architecture for Lifting-Based 2D DWT in JPEG2000.
MMM (2) 2007: 373-382 |
2006 |
6 | EE | Jinhui Xu,
Guiming Wu,
Yong Dou,
Yazhuo Dong:
Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining.
Asia-Pacific Computer Systems Architecture Conference 2006: 567-573 |
5 | EE | Song Lu,
BaoHua Fan,
Yong Dou,
Xiaodong Yang:
Clustering Multicast on Hypercube Network.
HPCC 2006: 61-70 |
4 | EE | Xue-Jun Yang,
Yong Dou,
Qing-Feng Hu:
Progress and Challenges in High Performance Computer Technology.
J. Comput. Sci. Technol. 21(5): 674-681 (2006) |
2005 |
3 | EE | YuXing Tang,
Kun Deng,
Xiaodong Wang,
Yong Dou,
Xingming Zhou:
RIMP: Runtime Implicit Predication.
APPT 2005: 71-80 |
2 | EE | Yong Dou,
Stamatis Vassiliadis,
Georgi Kuzmanov,
G. N. Gaydadjiev:
64-bit floating-point FPGA matrix multiplication.
FPGA 2005: 86-95 |
2003 |
1 | EE | Yong Dou,
Xicheng Lu:
LEAP: A Data Driven Loop Engine on Array Processor.
APPT 2003: 12-22 |