| |
| 2008 | ||
|---|---|---|
| 3 | EE | Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga: Synthesis of parallel prefix adders considering switching activities. ICCD 2008: 404-409 |
| 2007 | ||
| 2 | EE | Taeko Matsunaga, Yusuke Matsunaga: Area minimization algorithm for parallel prefix adders under bitwise delay constraints. ACM Great Lakes Symposium on VLSI 2007: 435-440 |
| 1 | EE | Taeko Matsunaga, Yusuke Matsunaga: Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders. IEICE Transactions 90-A(12): 2770-2777 (2007) |
| 1 | Shinji Kimura | [3] |
| 2 | Yusuke Matsunaga | [1] [2] [3] |