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Lasse Natvig

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2008
11EESabri Pllana, Siegfried Benkner, Eduard Mehofer, Lasse Natvig, Fatos Xhafa: Towards an Intelligent Environment for Programming Multi-core Computing Systems. Euro-Par Workshops 2008: 141-151
10EEMarius Grannæs, Magnus Jahre, Lasse Natvig: Low-cost open-page prefetch scheduling in chip multiprocessors. ICCD 2008: 390-396
2006
9EEHaakon Dybdahl, Marius Grannæs, Lasse Natvig: Cache Write-Back Schemes for Embedded Destructive-Read DRAM. ARCS 2006: 145-159
8EECyril Banino-Rokkones, Olivier Beaumont, Lasse Natvig: Master-Slave Tasking on Asymmetric Networks. Euro-Par 2006: 167-176
7EEHaakon Dybdahl, Per Stenström, Lasse Natvig: A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors. HiPC 2006: 22-34
6EEHaakon Dybdahl, Per Gunnar Kjeldsberg, Marius Grannæs, Lasse Natvig: Destructive-read in embedded DRAM, impact on power consumption. J. Embedded Computing 2(2): 249-260 (2006)
2004
5EELasse Natvig, Steinar Line: Age of computers: game-based teaching of computer fundamentals. ITiCSE 2004: 107-111
2001
4EELasse Natvig: Simulating Parallel Architectures with BSPlab. HPCN Europe 2001: 547-550
3EETormod Njølstad, Lasse Natvig: Experience from a 450 Students/Year Course on Digital Logic and Computer Fundamentals using FPGAs and mu-Controllers. MSE 2001: 18-19
1994
2 Lasse Natvig: Compile and Runtime Padding: An Approach to Realising Synchronous MIMD Execution. IFIP Congress (1) 1994: 553-558
1990
1EELasse Natvig: Logarithmic time cost optimal parallel sorting is not yet fast in practice!. SC 1990: 486-494

Coauthor Index

1Cyril Banino-Rokkones (Cyril Banino) [8]
2Olivier Beaumont [8]
3Siegfried Benkner [11]
4Haakon Dybdahl [6] [7] [9]
5Marius Grannæs [6] [9] [10]
6Magnus Jahre [10]
7Per Gunnar Kjeldsberg [6]
8Steinar Line [5]
9Eduard Mehofer [11]
10Tormod Njølstad [3]
11Sabri Pllana [11]
12Per Stenström [7]
13Fatos Xhafa [11]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)