| 2008 |
|---|
| 10 | EE | Eren Kursun,
Chen-Yong Cher:
Variation-aware thermal characterization and management of multi-core architectures.
ICCD 2008: 280-285 |
| 9 | EE | Carlos Boneti,
Francisco J. Cazorla,
Roberto Gioiosa,
Alper Buyuktosunoglu,
Chen-Yong Cher,
Mateo Valero:
Software-Controlled Priority Characterization of POWER5 Processor.
ISCA 2008: 415-426 |
| 8 | EE | Chen-Yong Cher,
Michael Gschwind:
Cell GC: using the cell synergistic processor as a garbage collection coprocessor.
VEE 2008: 141-150 |
| 2007 |
|---|
| 7 | EE | Jeonghwan Choi,
Chen-Yong Cher,
Hubertus Franke,
Henrdrik Hamann,
Alan J. Weger,
Pradip Bose:
Thermal-aware task scheduling at the system software level.
ISLPED 2007: 213-218 |
| 2006 |
|---|
| 6 | EE | Chen-Yong Cher,
Il Park,
T. N. Vijaykumar:
Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?.
ARCS 2006: 232-251 |
| 5 | EE | Canturk Isci,
Alper Buyuktosunoglu,
Chen-Yong Cher,
Pradip Bose,
Margaret Martonosi:
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget.
MICRO 2006: 347-358 |
| 2005 |
|---|
| 4 | EE | Hai Li,
Chen-Yong Cher,
Kaushik Roy,
T. N. Vijaykumar:
Combined circuit and architectural level variable supply-voltage scaling for low power.
IEEE Trans. VLSI Syst. 13(5): 564-576 (2005) |
| 2004 |
|---|
| 3 | EE | Chen-Yong Cher,
Antony L. Hosking,
T. N. Vijaykumar:
Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign.
ASPLOS 2004: 199-210 |
| 2003 |
|---|
| 2 | EE | Hai Li,
Chen-Yong Cher,
T. N. Vijaykumar,
Kaushik Roy:
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power.
MICRO 2003: 19-28 |
| 2001 |
|---|
| 1 | EE | Chen-Yong Cher,
T. N. Vijaykumar:
Skipper: a microarchitecture for exploiting control-flow independence.
MICRO 2001: 4-15 |
