| |
| 2008 | ||
|---|---|---|
| 2 | EE | Veerapaneni Nagbhushan, C. Y. Roger Chen: Modeling and reduction of complex timing constraints in high performance digital circuits. ICCD 2008: 544-550 |
| 2007 | ||
| 1 | EE | Veerapaneni Nagbhushan, C. Y. Roger Chen: Algorithms to simplify multi-clock/edge timing constraints. ICCD 2007: 444-449 |
| 1 | C. Y. Roger Chen | [1] [2] |