| 2008 |
|---|
| 8 | EE | Phiroze N. Parakh,
Shankar Krishnamoorthy:
A robust approach to lithography friendly design implementation.
ISPD 2008: 70 |
| 2004 |
|---|
| 7 | EE | Saurabh N. Adya,
Mehmet Can Yildiz,
Igor L. Markov,
Paul Villarrubia,
Phiroze N. Parakh,
Patrick H. Madden:
Benchmarking for large-scale placement and beyond.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 472-487 (2004) |
| 2003 |
|---|
| 6 | EE | Saurabh N. Adya,
Mehmet Can Yildiz,
Igor L. Markov,
Paul Villarrubia,
Phiroze N. Parakh,
Patrick H. Madden:
Benchmarking for large-scale placement and beyond.
ISPD 2003: 95-103 |
| 5 | EE | Navaratnasothie Selvakkumaran,
Phiroze N. Parakh,
George Karypis:
Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement.
SLIP 2003: 53-59 |
| 2000 |
|---|
| 4 | EE | Alan J. Drake,
Todd D. Basso,
Spencer M. Gold,
Keith L. Kraver,
Phiroze N. Parakh,
Claude R. Gauthier,
P. Sean Stetson,
Richard B. Brown:
CGaAs PowerPC FXU.
DAC 2000: 730-735 |
| 1999 |
|---|
| 3 | EE | Phiroze N. Parakh,
Richard B. Brown:
Crosstalk constrained global route embedding.
ISPD 1999: 201-206 |
| 1998 |
|---|
| 2 | EE | Phiroze N. Parakh,
Richard B. Brown,
Karem A. Sakallah:
Congestion Driven Quadratic Placement.
DAC 1998: 275-278 |
| 1 | EE | Richard B. Brown,
Bruce Bernhardt,
M. LaMacchia,
J. Abrokwah,
Phiroze N. Parakh,
Todd D. Basso,
Spencer M. Gold,
S. Stetson,
Claude R. Gauthier,
D. Foster,
B. Crawforth,
T. McQuire,
Karem A. Sakallah,
Ronald J. Lomax,
Trevor N. Mudge:
Overview of complementary GaAs technology for high-speed VLSI circuits.
IEEE Trans. VLSI Syst. 6(1): 47-51 (1998) |
