2008 |
12 | EE | Shufan Yang,
Steve Furber,
Yebin Shi,
Luis A. Plana:
An admission control system for QoS provision on a best-effort GALS interconnect.
ACSD 2008: 200-207 |
11 | EE | M. M. Khan,
D. R. Lester,
Luis A. Plana,
Alexander D. Rast,
X. Jin,
E. Painkras,
Stephen B. Furber:
SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor.
IJCNN 2008: 2849-2856 |
10 | EE | Luis A. Plana,
John Bainbridge,
Steve Furber,
Sean Salisbury,
Yebin Shi,
Jian Wu:
An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator.
NOCS 2008: 215-216 |
2007 |
9 | EE | Luis A. Plana,
Doug Edwards,
Sam Taylor,
Luis A. Tarazona,
Andrew Bardsley:
Performance-driven syntax-directed synthesis of asynchronous processors.
CASES 2007: 43-47 |
8 | EE | Luis A. Plana,
Stephen B. Furber,
Steve Temple,
Mukaram Khan,
Yebin Shi,
Jian Wu,
Shufan Yang:
A GALS Infrastructure for a Massively Parallel Multiprocessor.
IEEE Design & Test of Computers 24(5): 454-463 (2007) |
2005 |
7 | EE | Luis A. Plana,
Sam Taylor,
Doug Edwards:
Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance.
ICCD 2005: 703-710 |
2004 |
6 | EE | W. J. Bainbridge,
Luis A. Plana,
Stephen B. Furber:
The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip.
DATE 2004: 274-279 |
2003 |
5 | EE | Z. C. Yu,
Stephen B. Furber,
Luis A. Plana:
An Investigation into the Security of Self-Timed Circuits.
ASYNC 2003: 206-215 |
4 | EE | Luis A. Plana,
P. A. Riocreux,
W. J. Bainbridge,
Andrew Bardsley,
Steve Temple,
Jim D. Garside,
Z. C. Yu:
SPA - a secure Amulet core for smartcard applications.
Microprocessors and Microsystems 27(9): 431-446 (2003) |
2002 |
3 | EE | W. J. Bainbridge,
Andrew Bardsley,
Steve Temple,
Jim D. Garside,
P. A. Riocreux,
Luis A. Plana:
SPA - A Synthesisable Amulet Core for Smartcard pplications.
ASYNC 2002: 201-210 |
1998 |
2 | EE | Luis A. Plana,
Steven M. Nowick:
Architectural optimization for low-power nonpipelined asynchronous systems.
IEEE Trans. VLSI Syst. 6(1): 56-65 (1998) |
1996 |
1 | EE | Luis A. Plana,
Steven M. Nowick:
Concurrency-oriented optimization for low-power asynchronous systems.
ISLPED 1996: 151-156 |