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2000 | ||
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4 | EE | Chaitali Chakrabarti, Lori E. Lucke: VLSI architectures for weighted order statistic (WOS) filters. Signal Processing 80(8): 1419-1433 (2000) |
1998 | ||
3 | EE | K. Ito, Lori E. Lucke, Keshab K. Parhi: ILP-based cost-optimal DSP synthesis with module selection and data format conversion. IEEE Trans. VLSI Syst. 6(4): 582-594 (1998) |
1994 | ||
2 | EE | Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi: Module selection and data format conversion for cost-optimal DSP synthesis. ICCAD 1994: 322-329 |
1993 | ||
1 | EE | Lori E. Lucke, Keshab K. Parhi: Data-flow transformations for critical path time reduction in high-level DSP synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1063-1068 (1993) |
1 | Chaitali Chakrabarti | [4] |
2 | K. Ito | [3] |
3 | Kazuhito Ito | [2] |
4 | Keshab K. Parhi | [1] [2] [3] |