Moritoshi Yasunaga

2008
24	EE	Moritoshi Yasunaga, Yoshiki Yamaguchi, Hiroshi Nakayama, Ikuo Yoshihara, Naoki Koizumi, Jung Hwan Kim: The Segmental-Transmission-Line: Its Design and Prototype Evaluation. ICES 2008: 130-140
2007
23	EE	Kyrre Glette, Jim Torresen, Moritoshi Yasunaga: Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA. AHS 2007: 463-470
22	EE	Kyrre Glette, Jim Torresen, Moritoshi Yasunaga: An Online EHW Pattern Recognition System Applied to Face Image Recognition. EvoWorkshops 2007: 271-280
21	EE	Kyrre Glette, Jim Torresen, Moritoshi Yasunaga: An Online EHW Pattern Recognition System Applied to Sonar Spectrum Classification. ICES 2007: 1-12
20	EE	Yoshiki Yamaguchi, Noriyuki Aibe, Moritoshi Yasunaga, Yorihisa Yamamoto, Takaaki Awano, Ikuo Yoshihara: Bio-Inspired Functional Asymmetry Camera System. ICONIP (2) 2007: 637-646
19		Yusuke Arai, Ryo Sawai, Yoshiki Yamaguchi, Tsutomu Maruyama, Moritoshi Yasunaga: A Lattice Gas Cellular Automata Simulator on the Cell Broadband Engine. PARCO 2007: 459-466
18	EE	Hung Dinh Nguyen, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga: Implementation of an Effective Hybrid GA for Large-Scale Traveling Salesman Problems. IEEE Transactions on Systems, Man, and Cybernetics, Part B 37(1): 92-99 (2007)
17	EE	Hung Dinh Nguyen, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga: A New Three-Level Tree Data Structure for Representing TSP Tours in the Lin-Kernighan Heuristic. IEICE Transactions 90-A(10): 2187-2193 (2007)
16	EE	Yoshiki Yamaguchi, Tsutomu Maruyama, Ryuzo Azuma, Moritoshi Yasunaga, Akihiko Konagaya: Mesoscopic-level Simulation of Dynamics and Interactions of Biological Molecules Using Monte Carlo Simulation. VLSI Signal Processing 48(3): 287-299 (2007)
2006
15	EE	Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yoshiki Yamaguchi: On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition. AHS 2006: 373-380
2005
14	EE	Naoki Koizumi, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga: Variable length segmental-transmission-line and its parameter optimization based on GA. Congress on Evolutionary Computation 2005: 1576-1582
13	EE	Daekwan Seo, Moritoshi Yasunaga, Insook Kim, Byungwoon Ham, Jung Hwan Kim: Finding transcriptional regulatory elements in Dictyostelium gene expression. Congress on Evolutionary Computation 2005: 1746-1752
2003
12	EE	Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim: Gene Finding Using Evolvable Reasoning Hardware. ICES 2003: 198-207
2001
11		Yong Liu, Kiyoshi Tanaka, Masaya Iwata, Tetsuya Higuchi, Moritoshi Yasunaga: Evolvable Systems: From Biology to Hardware, 4th International Conference, ICES 2001 Tokyo, Japan, October 3-5, 2001, Proceedings Springer 2001
10		Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara: Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation. Genetic Programming and Evolvable Machines 2(3): 211-230 (2001)
2000
9	EE	Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim: A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI. DFT 2000: 69-77
8	EE	Moritoshi Yasunaga, Taro Nakamura, Jung Hwan Kim, Ikuo Yoshihara: Kernel-Based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables. Evolvable Hardware 2000: 253-262
7	EE	Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara: The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips. FPGA 2000: 116-125
6		Ikuo Yoshihara, Tomoo Aoyama, Moritoshi Yasunaga: A Fast Model-Building Method for Time Series Using Genetic Programming. GECCO 2000: 537
5	EE	Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, Jung Hwan Kim: Genetic Algorithm-Based Methodology for Pattern Recognition Hardware. ICES 2000: 264-273
1998
4		H. Koizumi, T. Ochiai, T. Okahashi, Y. Yamashita, A. Maki, T. Yamamoto, Y. Inagami, H. Yoshizawa, M. Iwata, Takashi Omori, Moritoshi Yasunaga: Dynamic Optical Topography and the Real-Time PDP Chip: An Analytical and Synthetical Approach to Higher-Order Brain Functions. ICONIP 1998: 337-340
3	EE	Moritoshi Yasunaga, Akio Yamada, T. Okahashi: Performance of a bus-based parallel computer with integer-representation processors applied to artificial neural network and parallel AI domains. KES (3) 1998: 519-527
2	EE	Moritoshi Yasunaga, I. Hachiya, K. Moki, Jung Hwan Kim: Fault-tolerant self-organizing map implemented by wafer-scale integration. IEEE Trans. VLSI Syst. 6(2): 257-265 (1998)
1992
1		Hiroaki Kitano, Moritoshi Yasunaga: Wafer Scale Integration for Massively Parallel Memory-Based Reasoning. AAAI 1992: 850-856

Coauthor Index

1	Noriyuki Aibe	[20]
2	Tomoo Aoyama	[6]
3	Yusuke Arai	[19]
4	Takaaki Awano	[20]
5	Ryuzo Azuma	[16]
6	Kyrre Glette	[15] [21] [22] [23]
7	I. Hachiya	[2]
8	Byungwoon Ham	[13]
9	Tetsuya Higuchi	[11]
10	Y. Inagami	[4]
11	M. Iwata	[4]
12	Masaya Iwata	[11]
13	Insook Kim	[13]
14	Jung Hwan Kim	[2] [5] [7] [8] [9] [10] [12] [13] [24]
15	Hiroaki Kitano	[1]
16	H. Koizumi	[4]
17	Naoki Koizumi	[14] [24]
18	Akihiko Konagaya	[16]
19	Yong Liu	[11]
20	A. Maki	[4]
21	Tsutomu Maruyama	[16] [19]
22	K. Moki	[2]
23	Taro Nakamura	[5] [8]
24	Hiroshi Nakayama	[24]
25	Hung Dinh Nguyen	[17] [18]
26	T. Ochiai	[4]
27	T. Okahashi	[3] [4]
28	Takashi Omori	[4]
29	Ryo Sawai	[19]
30	Daekwan Seo	[13]
31	Kiyoshi Tanaka	[11]
32	Jim Torresen	[15] [21] [22] [23]
33	Akio Yamada	[3]
34	Yoshiki Yamaguchi	[15] [16] [19] [20] [24]
35	Kunihito Yamamori	[14] [17] [18]
36	T. Yamamoto	[4]
37	Yorihisa Yamamoto	[20]
38	Y. Yamashita	[4]
39	Ikuo Yoshihara	[5] [6] [7] [8] [9] [10] [12] [14] [17] [18] [20] [24]
40	H. Yoshizawa	[4]

Colors in the list of coauthors