2008 | ||
---|---|---|
71 | EE | Roberto R. Osorio, Javier D. Bruguera: An FPGA architecture for CABAC decoding in manycore systems. ASAP 2008: 293-298 |
70 | EE | Hans-Joachim Bungartz, Javier D. Bruguera, Peter Arbenz, Bruce Hendrickson: Topic 10: Parallel Numerical Algorithms. Euro-Par 2008: 778-779 |
69 | EE | Alex Piñeiro, Javier D. Bruguera, Fabrizio Lamberti, Paolo Montuschi: A Radix-2 Digit-by-Digit Architecture for Cube Root. IEEE Trans. Computers 57(4): 562-566 (2008) |
2007 | ||
68 | EE | Roberto R. Osorio, Javier D. Bruguera: Entropy Coding on a Programmable Processor Array for Multimedia SoC. ASAP 2007: 222-227 |
67 | EE | Paolo Montuschi, Javier D. Bruguera, Luigi Ciminiera, José-Alejandro Piñeiro: A Digit-by-Digit Algorithm for mth Root Extraction. IEEE Trans. Computers 56(12): 1696-1706 (2007) |
66 | EE | F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera: Hardware support for adaptive tessellation of Bézier surfaces based on local tests. Journal of Systems Architecture 53(4): 233-250 (2007) |
2006 | ||
65 | EE | Viay Holimath, Javier D. Bruguera: A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table. DSD 2006: 236-239 |
64 | EE | Roberto R. Osorio, Javier D. Bruguera: A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems. DSD 2006: 269-274 |
63 | EE | Javier D. Bruguera, Roberto R. Osorio: A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. DSD 2006: 407-414 |
62 | EE | Roberto R. Osorio, Javier D. Bruguera: High-Throughput Architecture for H.264/AVC CABAC Compression System. IEEE Trans. Circuits Syst. Video Techn. 16(11): 1376-1384 (2006) |
2005 | ||
61 | EE | Roberto R. Osorio, Javier D. Bruguera: A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. DSD 2005: 298-305 |
60 | EE | Javier D. Bruguera, Tomás Lang: Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition. IEEE Symposium on Computer Arithmetic 2005: 42-51 |
59 | F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera: Adaptive Tessellation of Bezier Surfaces Based on Displacement Maps. WSCG (Short Papers) 2005: 29-32 | |
58 | EE | José-Alejandro Piñeiro, Stuart F. Oberman, Jean-Michel Muller, Javier D. Bruguera: High-Speed Function Approximation Using a Minimax Quadratic Interpolator. IEEE Trans. Computers 54(3): 304-318 (2005) |
57 | EE | José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation. VLSI Signal Processing 40(1): 109-123 (2005) |
2004 | ||
56 | EE | Roberto R. Osorio, Javier D. Bruguera: Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. DSD 2004: 62-69 |
55 | Paula N. Mallón, Montserrat Bóo, Margarita Amor, Javier D. Bruguera: Algorithms and Hardware for Data Compression in Point Rendering Applications. WSCG (Short Papers) 2004: 173-180 | |
54 | EE | Tomás Lang, Javier D. Bruguera: Floating-Point Multiply-Add-Fused with Reduced Latency. IEEE Trans. Computers 53(8): 988-1003 (2004) |
53 | EE | José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: Algorithm and Architecture for Logarithm, Exponential, and Powering Computation. IEEE Trans. Computers 53(9): 1085-1096 (2004) |
2003 | ||
52 | EE | José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: High-Radix Iterative Algorithm for Powering Computation. IEEE Symposium on Computer Arithmetic 2003: 204-211 |
51 | EE | José-Alejandro Piñeiro, Javier D. Bruguera, Milos D. Ercegovac: On-line high-radix exponential with selection by rounding. ISCAS (4) 2003: 121-124 |
50 | EE | F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera: Adaptive Tessellation of NURBS Surfaces. WSCG 2003 |
49 | EE | Juan Touriño, Jorge Parapar, Ramon Doallo, Marcos Boullón, Francisco F. Rivera, Javier D. Bruguera, Xesús P. González, Rafael Crecente, Carlos Álvarez: Research Article: A GIS-embedded system to support land consolidation plans in Galicia. International Journal of Geographical Information Science 17(4): 377-396 (2003) |
48 | EE | D. Piso, José-Alejandro Piñeiro, Javier D. Bruguera: Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor. Journal of Systems Architecture 49(12-15): 543-555 (2003) |
47 | EE | María J. Martín, David E. Singh, José Carlos Mouriño, Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera: High performance air pollution modeling for a power plant environment. Parallel Computing 29(11-12): 1763-1790 (2003) |
46 | EE | Javier D. Bruguera, Tomás Lang: Multilevel Reverse-Carry Addition: Single and Dual Adders. VLSI Signal Processing 33(1-2): 55-74 (2003) |
2002 | ||
45 | EE | Paula N. Mallón, Montserrat Bóo, Margarita Amor, Javier D. Bruguera: Concentric Strips: Algorithms and Architecture for the Compression/Decompression of Triangle Meshes. 3DPVT 2002: 380-383 |
44 | EE | José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: High-Radix Logarithm with Selection by Rounding. ASAP 2002: 101-110 |
43 | EE | D. Piso, José-Alejandro Piñeiro, Javier D. Bruguera: Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor. DSD 2002: 218-225 |
42 | EE | Ángel del Río, Montserrat Bóo, Margarita Amor, Javier D. Bruguera: Hardware Implementation of the Subdivision Loop Algorithm. EUROMICRO 2002: 189-199 |
41 | EE | José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. ICCD 2002: 132-137 |
40 | EE | Tomás Lang, Javier D. Bruguera: Floating-Point Fused Multiply-Add with Reduced Latency. ICCD 2002: 145- |
39 | EE | José-Alejandro Piñeiro, Javier D. Bruguera: High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root. IEEE Trans. Computers 51(12): 1377-1388 (2002) |
2001 | ||
38 | Juan Touriño, Francisco F. Rivera, Carlos Álvarez, Cesar M. Dans, Jorge Parapar, Ramon Doallo, Marcos Boullón, Javier D. Bruguera, Rafael Crecente, Xesús P. González: COPA: a GIS-based Tool for Land Consolidation Projects. ACM-GIS 2001: 53-58 | |
37 | EE | José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller: FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation. DSD 2001: 262-269 |
36 | EE | Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera: Implementation of a NURBS to Bézier Conversor with Constant Latency. FPL 2001: 213-222 |
35 | EE | José Carlos Mouriño, David E. Singh, María J. Martín, J. M. Eiroa, Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera: Parallelization of the STEM-II Air Quality Model. HPCN Europe 2001: 543-546 |
34 | EE | José Carlos Mouriño, María J. Martín, Ramon Doallo, David E. Singh, Francisco F. Rivera, Javier D. Bruguera: The STEM-II Air Quality Model on a Distributed Memory System. ICPP Workshops 2001: 85-92 |
33 | EE | Javier D. Bruguera, Tomás Lang: Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition. IEEE Symposium on Computer Arithmetic 2001: 203-210 |
32 | EE | José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller: Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree. IEEE Symposium on Computer Arithmetic 2001: 40- |
31 | EE | Javier D. Bruguera, Tomás Lang: Multilevel reverse most-significant carry computation. IEEE Trans. VLSI Syst. 9(6): 959-962 (2001) |
2000 | ||
30 | EE | Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera: Parallel Architecture for Conversion of NURBS Curves to Bézier Curves. EUROMICRO 2000: 1324-1331 |
29 | EE | Javier D. Bruguera, Tomás Lang: Multilevel Reverse-Carry Adder. ICCD 2000: 155-162 |
28 | EE | Elisardo Antelo, Tomás Lang, Javier D. Bruguera: Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring. IEEE Trans. Computers 49(7): 727-739 (2000) |
27 | EE | Elisardo Antelo, Tomás Lang, Javier D. Bruguera: Very-High Radix CORDIC Rotation Based on Selection by Rounding. VLSI Signal Processing 25(2): 141-153 (2000) |
1999 | ||
26 | EE | Tomás Lang, Javier D. Bruguera: Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. ICCD 1999: 73-79 |
25 | EE | Elisardo Antelo, Tomás Lang, Javier D. Bruguera: Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. IEEE Symposium on Computer Arithmetic 1999: 204- |
24 | Javier D. Bruguera, Tomás Lang: Leading-One Prediction with Concurrent Position Correction. IEEE Trans. Computers 48(10): 1083-1097 (1999) | |
1998 | ||
23 | EE | Roberto R. Osorio, Montserrat Bóo, Javier D. Bruguera: Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory. EUROMICRO 1998: 10139- |
22 | Elisardo Antelo, Tomás Lang, Javier D. Bruguera: Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling. IEEE Trans. Computers 47(2): 152-161 (1998) | |
21 | EE | Elisardo Antelo, Montserrat Bóo, Javier D. Bruguera, Emilio L. Zapata: A novel design of a two operand normalization circuit. IEEE Trans. VLSI Syst. 6(1): 173-176 (1998) |
20 | EE | Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera: Radix-4 Vectoring CORDIC Algorithm and Architectures. VLSI Signal Processing 19(2): 127-147 (1998) |
1997 | ||
19 | EE | Roberto R. Osorio, Javier D. Bruguera: New arithmetic coder/decoder architectures based on pipelining. ASAP 1997: 106-115 |
18 | EE | Mercedes Péon, Roberto R. Osorio, Javier D. Bruguera: A VLSI implementation of an arithmetic coder for image compression. EUROMICRO 1997: 591- |
17 | Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Emilio L. Zapata: Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm. IEEE Trans. Computers 46(11): 1264-1271 (1997) | |
16 | Elisardo Antelo, Julio Villalba, Javier D. Bruguera, Emilio L. Zapata: High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. IEEE Trans. Computers 46(8): 855-870 (1997) | |
15 | EE | Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata: Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures. VLSI Signal Processing 17(1): 57-73 (1997) |
1996 | ||
14 | EE | Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata: High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining. ASAP 1996: 165- |
13 | EE | Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera: Radix-4 Vectoring Cordic Algorithm And Architectures. ASAP 1996: 55-64 |
12 | Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata: High Radix Cordic Rotation Based on Selection by Rounding. Euro-Par, Vol. II 1996: 155-164 | |
11 | Elisardo Antelo, Javier D. Bruguera, Emilio L. Zapata: Unified Mixed Radix 2-4 Redundant CORDIC Processor. IEEE Trans. Computers 45(9): 1068-1073 (1996) | |
10 | EE | Javier D. Bruguera, Nicolas Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata: Cordic based parallel/pipelined architecture for the Hough transform. VLSI Signal Processing 12(3): 207-221 (1996) |
1995 | ||
9 | EE | Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata: Digit On-line Large Radix CORDIC Rotator. ASAP 1995: 246-257 |
8 | EE | Julio Villalba, J. A. Hidalgo, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera: CORDIC Architectures with Parallel Compensation of the Scale Factor. ASAP 1995: 258-269 |
7 | EE | Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata: Redundant CORDIC Rotator Based on Parallel Prediction. IEEE Symposium on Computer Arithmetic 1995: 172-179 |
6 | EE | Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata: A Parallel Architecture for the Self-Sorting FFT Algorithm. J. Parallel Distrib. Comput. 31(1): 88-97 (1995) |
1994 | ||
5 | EE | Francisco Argüello, Javier D. Bruguera, Ramon Doallo, Emilio L. Zapata: Parallel Architecture for Fast Transforms with Trigonometric Kernel. IEEE Trans. Parallel Distrib. Syst. 5(10): 1091-1099 (1994) |
1993 | ||
4 | Javier D. Bruguera, Elisardo Antelo, Emilio L. Zapata: Design of a Pipelined Radix 4 CORDIC Processor. Parallel Computing 19(7): 729-744 (1993) | |
1990 | ||
3 | Oscar G. Plata, Javier D. Bruguera, Francisco F. Rivera, Ramon Doallo, Emilio L. Zapata: ACLE: A Software Package for SIMD Computer Simulation. Comput. J. 33(3): 194-203 (1990) | |
2 | Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera, Emilio L. Zapata, R. Peskin: Gaussian elimination with pivoting on hypercubes. Parallel Computing 14(1): 51-60 (1990) | |
1 | Inmaculada García, Juan J. Merelo Guervós, Javier D. Bruguera, Emilio L. Zapata: Parallel quadrant interlocking factorization on hypercube computers. Parallel Computing 15(1-3): 87-100 (1990) |