| 2008 |
|---|
| 23 | EE | Moritoshi Yasunaga,
Yoshiki Yamaguchi,
Hiroshi Nakayama,
Ikuo Yoshihara,
Naoki Koizumi,
Jung Hwan Kim:
The Segmental-Transmission-Line: Its Design and Prototype Evaluation.
ICES 2008: 130-140 |
| 2005 |
|---|
| 22 | EE | Daekwan Seo,
Moritoshi Yasunaga,
Insook Kim,
Byungwoon Ham,
Jung Hwan Kim:
Finding transcriptional regulatory elements in Dictyostelium gene expression.
Congress on Evolutionary Computation 2005: 1746-1752 |
| 21 | EE | Jung Hwan Kim,
Sung-Soon Choi,
Byung Ro Moon:
Normalization for neural network in genetic search.
GECCO 2005: 1581-1582 |
| 2004 |
|---|
| 20 | EE | Jung Hwan Kim,
Sung-Soon Choi,
Byung Ro Moon:
Neural Network Normalization for Genetic Search.
GECCO (2) 2004: 398-399 |
| 2003 |
|---|
| 19 | EE | Jung Hwan Kim,
Byung Ro Moon:
New Usage of SOM for Genetic Algorithms.
GECCO 2003: 1101-1111 |
| 18 | EE | Moritoshi Yasunaga,
Ikuo Yoshihara,
Jung Hwan Kim:
Gene Finding Using Evolvable Reasoning Hardware.
ICES 2003: 198-207 |
| 2002 |
|---|
| 17 | | Jung Hwan Kim,
Byung Ro Moon:
Neuron Reordering For Better Neuro-genetic Hybrids.
GECCO 2002: 407-414 |
| 2001 |
|---|
| 16 | | Moritoshi Yasunaga,
Jung Hwan Kim,
Ikuo Yoshihara:
Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation.
Genetic Programming and Evolvable Machines 2(3): 211-230 (2001) |
| 2000 |
|---|
| 15 | EE | Moritoshi Yasunaga,
Ikuo Yoshihara,
Jung Hwan Kim:
A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI.
DFT 2000: 69-77 |
| 14 | EE | Moritoshi Yasunaga,
Taro Nakamura,
Jung Hwan Kim,
Ikuo Yoshihara:
Kernel-Based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables.
Evolvable Hardware 2000: 253-262 |
| 13 | EE | Moritoshi Yasunaga,
Jung Hwan Kim,
Ikuo Yoshihara:
The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips.
FPGA 2000: 116-125 |
| 12 | | Michael Yasunaga,
Taro Nakamura,
Ikuo Yoshihara,
Jung Hwan Kim:
Kernel Optimization in Pattern Recognition Using a Genetic Algorithm.
GECCO 2000: 391 |
| 11 | | Jung Hwan Kim,
Byung Ro Moon:
Genetic Elevator Group Control.
GECCO 2000: 762 |
| 10 | EE | Moritoshi Yasunaga,
Taro Nakamura,
Ikuo Yoshihara,
Jung Hwan Kim:
Genetic Algorithm-Based Methodology for Pattern Recognition Hardware.
ICES 2000: 264-273 |
| 1998 |
|---|
| 9 | EE | Moritoshi Yasunaga,
I. Hachiya,
K. Moki,
Jung Hwan Kim:
Fault-tolerant self-organizing map implemented by wafer-scale integration.
IEEE Trans. VLSI Syst. 6(2): 257-265 (1998) |
| 1994 |
|---|
| 8 | | Dah-Yea Wei,
Jung Hwan Kim,
T. R. N. Rao:
Roundoff Error-Free Tests in Algorithm-Based Fault Tolerant Matrix Operations on 2-D Processor Arrays.
DFT 1994: 74-82 |
| 7 | | Harold Szu,
Jung Hwan Kim,
Insook Kim:
Live neural network formations on electronic chips.
Neurocomputing 6(5): 551-564 (1994) |
| 1993 |
|---|
| 6 | | Dah-Yea Wei,
Jung Hwan Kim,
T. R. N. Rao:
Complete Tests in Algorithm-Based Fault-Tolerant Matrix Operations on Processor Arrays.
DFT 1993: 255-262 |
| 5 | | Jung Hwan Kim,
Phill K. Rhee:
The Rule-Based Approach to Reconfiguration of 2-D Processor Arrays.
IEEE Trans. Computers 42(11): 1403-1408 (1993) |
| 1992 |
|---|
| 4 | EE | Jung Hwan Kim,
Phill K. Rhee:
A resource-efficient reconfiguration algorithm of VLSI 2-D processor arrays.
VLSI Signal Processing 4(4): 317-330 (1992) |
| 1991 |
|---|
| 3 | | Jung Hwan Kim,
Phill K. Rhee:
A Parallel Reconfiguration Algorithm for WSI/VLSI Processor Arrays.
ICPP (1) 1991: 670-671 |
| 1989 |
|---|
| 2 | | Jung Hwan Kim,
Sudhakar M. Reddy:
On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement.
IEEE Trans. Computers 38(4): 515- (1989) |
| 1986 |
|---|
| 1 | | Jung Hwan Kim:
On-Line Detection of Errors in Homogeneous Multiprocessor Systems.
IEEE Real-Time Systems Symposium 1986: 55-62 |
