| |
| 1999 | ||
|---|---|---|
| 2 | H. Tabuchi, T. Yamada, M. Usami, M. Nagao, K. Moki, T. Ochiai, M. Kawai: Extending the Application of a Neural Network for Failure Analysis of Electronic Circuit Boards. IIA/SOCO 1999 | |
| 1998 | ||
| 1 | EE | Moritoshi Yasunaga, I. Hachiya, K. Moki, Jung Hwan Kim: Fault-tolerant self-organizing map implemented by wafer-scale integration. IEEE Trans. VLSI Syst. 6(2): 257-265 (1998) |
| 1 | I. Hachiya | [1] |
| 2 | M. Kawai | [2] |
| 3 | Jung Hwan Kim | [1] |
| 4 | M. Nagao | [2] |
| 5 | T. Ochiai | [2] |
| 6 | H. Tabuchi | [2] |
| 7 | M. Usami | [2] |
| 8 | T. Yamada | [2] |
| 9 | Moritoshi Yasunaga | [1] |