| |
| 1990 | ||
|---|---|---|
| 3 | EE | R. Ernst, S. Sutarwala, J.-Y. Jou, M. Tong: Simulation based verification of register-transfer level behavioral synthesis tools. EURO-DAC 1990: 396-400 |
| 1989 | ||
| 2 | R. Ernst, S. Sutarwala, J.-Y. Jou: TSG: A Test System Generator for Debugging and Regression Test of High-Level Behavioral Synthesis Tools. ITC 1989: 937 | |
| 1988 | ||
| 1 | M. Balakrishnan, S. Sutarwala, Arun K. Majumdar, Dilip K. Banerji, James G. Linders: A Semantic Approach for Modular Synthesis of VLSI Systems. Inf. Process. Lett. 27(1): 1-7 (1988) | |
| 1 | M. Balakrishnan | [1] |
| 2 | Dilip K. Banerji | [1] |
| 3 | R. Ernst | [2] [3] |
| 4 | J.-Y. Jou | [2] [3] |
| 5 | James G. Linders | [1] |
| 6 | Arun K. Majumdar | [1] |
| 7 | M. Tong | [3] |