| |
| 1999 | ||
|---|---|---|
| 2 | EE | Chaeryung Park, Taewhan Park, C. L. Liu: An efficient data path synthesis algorithm for behavioral-level power optimization. ISCAS (1) 1999: 294-297 |
| 1998 | ||
| 1 | EE | Chaeryung Park, Taewhan Kim, C. L. Liu: Register Allocation - A Hierarchical Reduction Approach. VLSI Signal Processing 19(3): 269-285 (1998) |
| 1 | Taewhan Kim | [1] |
| 2 | C. L. Liu (Chung Laung (Dave) Liu) | [1] [2] |
| 3 | Taewhan Park | [2] |