| 2008 |
|---|
| 7 | EE | Hwang-Cherng Chow,
Pu-Nan Weng:
A Low Voltage Rail-to-Rail OPAMP Design for Biomedical Signal Filtering Applications.
DELTA 2008: 232-235 |
| 2005 |
|---|
| 6 | EE | Hwang-Cherng Chow,
Bo-Wei Chen,
Hsiao-Chen Chen,
Wu-Shiung Feng:
A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications.
ISCAS (1) 2005: 736-739 |
| 2004 |
|---|
| 5 | | Hwang-Cherng Chow,
Shu-Hsien Chang:
High performance sense amplifier circuit for low power SRAM applications.
ISCAS (2) 2004: 741-744 |
| 2003 |
|---|
| 4 | EE | Hwang-Cherng Chow,
I-Chyn Wey:
A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder.
ISCAS (5) 2003: 121-124 |
| 2002 |
|---|
| 3 | EE | Hwang-Cherng Chow,
I-Chyn Wey:
A 3.3 V 1 GHz high speed pipelined Booth multiplier.
ISCAS (1) 2002: 457-460 |
| 2 | EE | Hwang-Cherng Chow,
Yung-Kuo Ho:
New pixel-shared design and split-path readout of CMOS image sensor circuits.
ISCAS (4) 2002: 49-52 |
| 1999 |
|---|
| 1 | EE | Hwang-Cherng Chow:
Bidirectional buffer for mixed voltage applications.
ISCAS (1) 1999: 270-273 |
