2009 | ||
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17 | EE | Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne: Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Transactions on Computational Science 4: 230-243 (2009) |
2008 | ||
16 | EE | Seyed Hosein Attarzadeh Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Design space exploration for field programmable compressor trees. CASES 2008: 207-216 |
15 | EE | Carlotta Guiducci, Alexandre Schmid, Frank K. Gürkaynak, Yusuf Leblebici: Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces. DATE 2008: 1328-1333 |
14 | EE | Stéphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Gürkaynak, Yusuf Leblebici: A Generic Standard Cell Design Methodology for Differential Circuit Styles. DATE 2008: 843-848 |
13 | EE | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190 |
12 | EE | Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer: Improving the power-delay product in SCL circuits using source follower output stage. ISCAS 2008: 145-148 |
2007 | ||
11 | EE | Milos Stanisavljevic, Frank K. Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani: Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density. ACM Great Lakes Symposium on VLSI 2007: 204-207 |
10 | EE | Milos Krstic, Eckhard Grass, Frank K. Gürkaynak, Pascal Vivet: Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook. IEEE Design & Test of Computers 24(5): 430-441 (2007) |
2006 | ||
9 | EE | Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner: GALS at ETH Zurich: Success or Failure. ASYNC 2006: 150-159 |
8 | EE | Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner: Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. Electr. Notes Theor. Comput. Sci. 146(2): 133-149 (2006) |
2004 | ||
7 | EE | Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, F. Hug, Hubert Kaeslin: A 2 Gb/s balanced AES crypto-chip implementation. ACM Great Lakes Symposium on VLSI 2004: 39-44 |
6 | EE | Siddika Berna Örs, Frank K. Gürkaynak, Elisabeth Oswald, Bart Preneel: Power-Analysis Attack on an ASIC AES implementation. ITCC (2) 2004: 546-552 |
2003 | ||
5 | EE | Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner: Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. ASYNC 2003: 141-150 |
4 | EE | Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner: Variable delay ripple carry adder with carry chain interrupt detection. ISCAS (5) 2003: 113-116 |
2002 | ||
3 | EE | Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner: A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. ASYNC 2002: 181-189 |
2 | EE | A. K. Lutz, J. Treichler, Frank K. Gürkaynak, Hubert Kaeslin, G. Basler, Antonia Erni, S. Reichmuth, P. Rommens, Stephan Oetiker, Wolfgang Fichtner: 2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. CHES 2002: 144-158 |
1999 | ||
1 | EE | Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici: Realization of a programmable rank-order filter architecture using capacitive threshold logic gates. ISCAS (1) 1999: 435-438 |