| 2001 |
|---|
| 7 | EE | R. V. K. Pillai,
Dhamin Al-Khalili,
Asim J. Al-Khalili,
S. Y. A. Shah:
A Low Power Approach to Floating Point Adder Design for DSP Applications.
VLSI Signal Processing 27(3): 195-213 (2001) |
| 1999 |
|---|
| 6 | EE | R. V. K. Pillai,
Dhamin Al-Khalili,
Asim J. Al-Khalili:
Power implications of precision limited arithmetic in floating point FIR filters.
ISCAS (1) 1999: 165-168 |
| 5 | | R. V. K. Pillai,
Dhamin Al-Khalili,
Asim J. Al-Khalili:
An IEEE Compliant Floating Point MAF.
VLSI 1999: 149-160 |
| 1998 |
|---|
| 4 | EE | R. V. K. Pillai,
Asim J. Al-Khalili,
Dhamin Al-Khalili:
A Low Power Floating Point Accumulator.
VLSI Design 1998: 330- |
| 1997 |
|---|
| 3 | | R. V. K. Pillai,
Dhamin Al-Khalili,
Asim J. Al-Khalili:
A Low Power Approach to Floating Point Adder Design.
ICCD 1997: 178-185 |
| 2 | EE | R. V. K. Pillai,
Dhamin Al-Khalili,
Asim J. Al-Khalili:
Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition.
ISLPED 1997: 235-238 |
| 1996 |
|---|
| 1 | EE | R. V. K. Pillai,
Dhamin Al-Khalili,
Asim J. Al-Khalili:
Energy delay analysis of partial product reduction methods for parallel multiplier implementation.
ISLPED 1996: 201-204 |
