| 2008 |
|---|
| 22 | EE | Tsung-Ta Lin,
Jen-Shiun Chiang:
Low cost architecture for JPEG2000 encoder without code-block memory.
ICME 2008: 137-140 |
| 21 | EE | Jen-Shiun Chiang,
Ting-Hao Hwang,
Tsung-Ta Lin,
Chih-Hsien Hsia:
High efficiency architecture of escot with pass concurrent context modeling scheme for scalable video coding.
ISCAS 2008: 2801-2804 |
| 2007 |
|---|
| 20 | EE | Hsin-Chuan Chen,
Jen-Shiun Chiang:
A High-Performance Sequential MRU Cache Using Valid-Bit Assistant Search Algorithm.
Journal of Circuits, Systems, and Computers 16(4): 613-626 (2007) |
| 2006 |
|---|
| 19 | EE | Jen-Shiun Chiang,
Yi-Tsung Li,
Hsin-Liang Chen:
A 20-MS/s sigma delta modulator for 802.11a applications.
ISCAS 2006 |
| 18 | EE | Jen-Shiun Chiang,
Chang-Yo Hsieh,
Jin-Chan Liu,
Cheng-Chih Chien:
Concurrent bit-plane coding architecture for EBCOT in JPEG2000.
ISCAS 2006 |
| 2005 |
|---|
| 17 | EE | Hsin-Chuan Chen,
Jen-Shiun Chiang:
Low-Power Way-Predicting Cache Using Valid-Bit Pre-Decision for Parallel Architectures.
AINA 2005: 203-206 |
| 16 | | Jen-Shiun Chiang,
Chih-Hsien Hsia,
Hsin-Jung Chen:
2-D Discrete Wavelet Transform with Efficient Lifting-Based Scheme.
CISST 2005: 193-197 |
| 15 | | Jen-Shiun Chiang,
Sin-Guo Jhou,
Yen-Jen Chen,
Je-Yu Tzou:
Temporal-Correlaction for Separating Block PSNR to Evaluate Video Coding Quality.
CISST 2005: 20-26 |
| 14 | EE | Jen-Shiun Chiang,
Chih-Hsien Hsia,
Hsin-Jung Chen,
Te-Jung Lo:
VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications.
ISCAS (5) 2005: 4554-4557 |
| 2004 |
|---|
| 13 | | Fun Ye,
Jen-Shiun Chiang,
Chun-Cheng Wu:
Low Power Sigma-Delta Modulator with Dynamic Biasing for Speech CODECs.
ESA/VLSI 2004: 31-35 |
| 12 | | Cheng-Chih Chien,
Jen-Shiun Chiang,
Ming-Hung Tu,
Yu-Cheng Sung,
Yi-Tsung Lee:
Low-Power Switched-Capacitor Filters for Telecommunication Applications.
ESA/VLSI 2004: 36-39 |
| 11 | EE | Jen-Shiun Chiang,
Chun-Hau Chang,
Yu-Sen Lin,
Chang-You Hsieh,
Chih-Hsieh Hsia:
High-speed EBCOT with dual context-modeling coding architecture for JPEG2000.
ISCAS (3) 2004: 865-868 |
| 10 | EE | Hsin-Chuan Chen,
Jen-Shiun Chiang:
A low-jitter phase-interpolation DDS using dual-slope integration.
IEICE Electronic Express 1(12): 333-338 (2004) |
| 2003 |
|---|
| 9 | EE | Jen-Shiun Chiang,
Ying-Hong Wang,
Chih-Hsiao Tsai,
Chih-Peng Hsu:
Location Management and Multimedia Communication Service Based on Mobile IP and Cellular IP Network.
AINA 2003: 223-228 |
| 8 | EE | Ying-Hong Wang,
Chen-An Wang,
Jen-Shiun Chiang,
Wen-Hung Lo:
A Secure Model in Agent-Based Marketplace.
AINA 2003: 302-305 |
| 7 | | Jen-Shiun Chiang,
Hsin-Liang Chen:
A MASH Sigme-Delta Modulator with Low-Distortion Architecture.
Embedded Systems and Applications 2003: 243-247 |
| 6 | EE | Jen-Shiun Chiang,
Hsueh-Ping Chen,
Cheng-ming Ying:
A 1V 0.54µW fourth order switched capacitor filter with switched opamp technique for cardiac pacemaker sensing channel.
ISCAS (1) 2003: 481-484 |
| 5 | EE | Jen-Shiun Chiang,
Pao-Chu Chou,
Teng-Hung Chang:
Dual-mode sigma-delta modulator for wideband receiver applications.
ISCAS (1) 2003: 997-1000 |
| 4 | EE | Jen-Shiun Chiang,
Min-Shiou Tsai:
A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling.
VLSI Signal Processing 33(1-2): 117-124 (2003) |
| 2002 |
|---|
| 3 | EE | Jen-Shiun Chiang,
Yu-Sen Lin,
Chang-Yo Hsieh:
Efficient pass-parallel architecture for EBCOT in JPEG2000.
ISCAS (1) 2002: 773-776 |
| 1999 |
|---|
| 2 | EE | Jen-Shiun Chiang,
Jian-Kao Chen:
An efficient VLSI architecture for RSA public-key cryptosystem.
ISCAS (1) 1999: 496-499 |
| 1992 |
|---|
| 1 | | Mi Lu,
Jen-Shiun Chiang:
A Novel Division Algorithm for the Residue Number System.
IEEE Trans. Computers 41(8): 1026-1032 (1992) |
