2009 |
42 | EE | Mladen Berekovic,
Christian Müller-Schloer,
Christian Hochberger,
Stephan Wong:
Architecture of Computing Systems - ARCS 2009, 22nd International Conference, Delft, The Netherlands, March 10-13, 2009. Proceedings
Springer 2009 |
2008 |
41 | | Mladen Berekovic,
Nikitas J. Dimopoulos,
Stephan Wong:
Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings
Springer 2008 |
40 | EE | Andres Garcia,
Mladen Berekovic,
Tom Vander Aa:
Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor.
ASAP 2008: 245-250 |
39 | EE | Frederico Pratas,
Georgi Gaydadjiev,
Mladen Berekovic,
Leonel Sousa,
Stefanos Kaxiras:
Low power microarchitecture with instruction reuse.
Conf. Computing Frontiers 2008: 149-158 |
38 | EE | Frank Bouwens,
Mladen Berekovic,
Bjorn De Sutter,
Georgi Gaydadjiev:
Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array.
HiPEAC 2008: 66-81 |
37 | EE | Jochem Govers,
Jos Huisken,
Mladen Berekovic,
Olivier Rousseaux,
Frank Bouwens,
Michael De Nil,
Jef L. van Meerbergen:
Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP.
HiPEAC 2008: 82-96 |
36 | EE | Mladen Berekovic,
Frank Bouwens,
Tom Vander Aa,
Diederik Verkest:
Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor.
PATMOS 2008: 449-457 |
35 | EE | Mladen Berekovic,
Christian Hochberger,
Andreas Koch:
Rekonfigurierbare Architekturen.
Informatik Spektrum 31(4): 344-347 (2008) |
34 | EE | Mladen Berekovic,
Andy D. Pimentel,
Timo D. Hämäläinen:
Editorial.
Journal of Systems Architecture - Embedded Systems Design 54(11): 1017-1018 (2008) |
33 | EE | Mladen Berekovic,
Mladen Berekovic,
Tim Niggemeier:
A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance.
Signal Processing Systems 50(2): 201-229 (2008) |
32 | EE | Mladen Berekovic,
Mladen Berekovic,
Tim Niggemeier:
A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance.
Signal Processing Systems 50(2): 201-229 (2008) |
2007 |
31 | | Stamatis Vassiliadis,
Mladen Berekovic,
Timo D. Hämäläinen:
Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings
Springer 2007 |
30 | EE | Frank Bouwens,
Mladen Berekovic,
Andreas Kanstein,
Georgi Gaydadjiev:
Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array.
ARC 2007: 1-13 |
29 | EE | Kehuai Wu,
Andreas Kanstein,
Jan Madsen,
Mladen Berekovic:
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture.
ARC 2007: 26-38 |
28 | EE | C. Arbelo,
Andreas Kanstein,
Sebastián López,
José Francisco López,
Mladen Berekovic,
Roberto Sarmiento,
Jean-Yves Mignolet:
Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter.
DATE 2007: 177-182 |
27 | EE | Mladen Berekovic:
Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical Monitoring.
DSD 2007: 16-18 |
26 | EE | M. Hartmann,
V. Pantazis,
Tom Vander Aa,
Mladen Berekovic,
Christian Hochberger,
Bjorn De Sutter:
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures.
ESTImedia 2007: 67-72 |
25 | EE | Lennart Yseboodt,
Michael De Nil,
Mladen Berekovic:
Electrocardiogram on Wireless Sensor Nodes.
Power-aware Computing Systems 2007 |
24 | EE | Lennart Yseboodt,
Michael De Nil,
Jos Huisken,
Mladen Berekovic,
Qin Zhao,
Frank Bouwens,
Jef L. van Meerbergen:
Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring.
SAMOS 2007: 385-395 |
2006 |
23 | EE | Bjorn De Sutter,
Bingfeng Mei,
Andrei Bartic,
Tom Vander Aa,
Mladen Berekovic,
Jean-Yves Mignolet,
Kris Croes,
Paul Coene,
Miro Cupac,
Aïssa Couvreur,
Andy Folens,
Steven Dupont,
Bert Van Thielen,
Andreas Kanstein,
Hong-Seok Kim,
Suk Jin Kim:
Hardware and a Tool Chain for ADRES.
ARC 2006: 425-430 |
22 | EE | Mladen Berekovic,
Tim Niggemeier:
A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme.
SAMOS 2006: 289-298 |
2005 |
21 | EE | Hans-Joachim Stolberg,
Mladen Berekovic,
Sören Moch,
Lars Friebe,
Mark Bernd Kulaczewski,
Sebastian Flügel,
Heiko Klußmann,
Andreas Dehnhardt,
Peter Pirsch:
HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing.
VLSI Signal Processing 41(1): 9-20 (2005) |
20 | EE | Hans-Joachim Stolberg,
Mladen Berekovic,
Peter Pirsch:
A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications.
VLSI Signal Processing 41(2): 139-151 (2005) |
2004 |
19 | EE | Sören Moch,
Mladen Berekovic,
Hans-Joachim Stolberg,
Lars Friebe,
Mark Bernd Kulaczewski,
Andreas Dehnhardt,
Peter Pirsch:
HIBRID-SOC: a multi-core architecture for image and video applications.
SIGARCH Computer Architecture News 32(3): 55-61 (2004) |
18 | EE | Mladen Berekovic,
Sören Moch,
Peter Pirsch:
A scalable, clustered SMT processor for digital signal processing.
SIGARCH Computer Architecture News 32(3): 62-69 (2004) |
2003 |
17 | EE | Hans-Joachim Stolberg,
Mladen Berekovic,
Lars Friebe,
Sören Moch,
Sebastian Flügel,
Xun Mao,
Mark Bernd Kulaczewski,
Heiko Klußmann,
Peter Pirsch:
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications.
DATE 2003: 20008-20013 |
16 | | Hans-Joachim Stolberg,
Mladen Berekovic,
Lars Friebe,
Sören Moch,
Sebastian Flügel,
Mark Bernd Kulaczewski,
Peter Pirsch:
HiBRID-SoC: a multi-core architecture for image and video applications.
ICIP (3) 2003: 101-104 |
15 | | Hans-Joachim Stolberg,
Mladen Berekovic,
Lars Friebe,
Sören Moch,
Mark Bernd Kulaczewski,
Peter Pirsch:
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing.
VLSI-SOC 2003: 155-160 |
2002 |
14 | | Mladen Berekovic,
Hans-Joachim Stolberg,
Peter Pirsch:
Multicore system-on-chip architecture for MPEG-4 streaming video.
IEEE Trans. Circuits Syst. Video Techn. 12(8): 688- (2002) |
13 | EE | Mladen Berekovic,
Peter Pirsch,
Thorsten Selinger,
Kai-Immo Wels,
Carolina Miro,
Anne Lafage,
Christoph Heer,
Giovanni Ghigo:
Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing.
VLSI Signal Processing 31(2): 157-171 (2002) |
2001 |
12 | EE | Hans-Joachim Stolberg,
Mladen Berekovic,
Peter Pirsch,
Holger Runge:
Implementing The MPEG-4 Advanced Simple Profile For Streaming Video Applications.
ICME 2001 |
2000 |
11 | EE | Mladen Berekovic,
Peter Pirsch,
Thorsten Selinger,
Kai-Immo Wels,
Carolina Miro,
Anne Lafage,
Christoph Heer,
Giovanni Ghigo:
Architecture of an Image Rendering Co-Processor for MPEG-4 Systems.
ASAP 2000: 15-24 |
10 | | Christoph Heer,
Carolina Miro,
Anne Lafage,
Mladen Berekovic,
Giovanni Ghigo,
Thorsten Selinger,
Kai-Immo Wels:
Coprocessor architecture for MPEG-4 video object rendering.
VCIP 2000: 1451-1458 |
1999 |
9 | | Helge Kloos,
Mladen Berekovic,
Peter Pirsch:
Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen.
ARCS 1999: 5-14 |
8 | EE | Mladen Berekovic,
K. Jacob,
Peter Pirsch:
Architecture of a hardware module for MPEG-4 shape decoding.
ISCAS (1) 1999: 157-160 |
7 | EE | Mladen Berekovic,
Helge Kloos,
Peter Pirsch:
Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications.
VLSI Signal Processing 22(1): 31-43 (1999) |
6 | EE | Mladen Berekovic,
Hans-Joachim Stolberg,
Mark Bernd Kulaczewski,
Peter Pirsch,
Henning Möller,
Holger Runge,
Johannes Kneip,
Benno Stabernack:
Instruction Set Extensions for MPEG-4 Video.
VLSI Signal Processing 23(1): 27-49 (1999) |
5 | EE | S. Bauer,
Johannes Kneip,
T. Mlasko,
Bernd Schmale,
J. Vollmer,
A. Hutter,
Mladen Berekovic:
The MPEG-4 Multimedia Coding Standard: Algorithms, Architectures and Applications.
VLSI Signal Processing 23(1): 7-26 (1999) |
1998 |
4 | EE | Mladen Berekovic,
Peter Pirsch:
An Array Processor Architecture with Parallel Data Cache for Image Rendering and Compositing.
Computer Graphics International 1998: 411- |
3 | EE | Jens Peter Wittenburg,
Willm Hinrichs,
Johannes Kneip,
Martin Ohmacht,
Mladen Berekovic,
Hanno Lieske,
Helge Kloos,
Peter Pirsch:
Realization of a Programmable Parallel DSP for High Performance Image Processing Applications.
DAC 1998: 56-61 |
2 | EE | Mladen Berekovic,
Peter Pirsch,
Johannes Kneip:
An Algorithm-Hardware-System Approach to VLIW Multimedia Processors.
VLSI Signal Processing 20(1-2): 163-180 (1998) |
1997 |
1 | EE | Johannes Kneip,
Mladen Berekovic,
Jens Peter Wittenburg,
Willm Hinrichs,
Peter Pirsch:
An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor.
VLSI Signal Processing 16(1): 31-40 (1997) |