| 2009 |
|---|
| 7 | EE | Yi Zhu,
Yuanfang Hu,
Michael Bedford Taylor,
Chung-Kuan Cheng:
Energy and switch area optimizations for FPGA global routing architectures.
ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
| 2007 |
|---|
| 6 | EE | Yuanfang Hu,
Yi Zhu,
Michael Bedford Taylor,
Chung-Kuan Cheng:
FPGA global routing architecture optimization using a multicommodity flow approach.
ICCD 2007: 144-151 |
| 2005 |
|---|
| 5 | EE | Michael Bedford Taylor,
Walter Lee,
Saman P. Amarasinghe,
Anant Agarwal:
Scalar Operand Networks.
IEEE Trans. Parallel Distrib. Syst. 16(2): 145-162 (2005) |
| 2004 |
|---|
| 4 | EE | Michael Bedford Taylor,
Walter Lee,
Jason E. Miller,
David Wentzlaff,
Ian Bratt,
Ben Greenwald,
Henry Hoffmann,
Paul Johnson,
Jason Sungtae Kim,
James Psota,
Arvind Saraf,
Nathan Shnidman,
Volker Strumpen,
Matthew Frank,
Saman P. Amarasinghe,
Anant Agarwal:
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams.
ISCA 2004: 2-13 |
| 2003 |
|---|
| 3 | EE | Michael Bedford Taylor,
Walter Lee,
Saman P. Amarasinghe,
Anant Agarwal:
Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture.
HPCA 2003: 341-353 |
| 2 | EE | Jason Sungtae Kim,
Michael Bedford Taylor,
Jason E. Miller,
David Wentzlaff:
Energy characterization of a tiled architecture processor with on-chip networks.
ISLPED 2003: 424-427 |
| 2002 |
|---|
| 1 | EE | Michael Bedford Taylor,
Jason Sungtae Kim,
Jason E. Miller,
David Wentzlaff,
Fae Ghodrat,
Ben Greenwald,
Henry Hoffmann,
Paul Johnson,
Jae-Wook Lee,
Walter Lee,
Albert Ma,
Arvind Saraf,
Mark Seneski,
Nathan Shnidman,
Volker Strumpen,
Matthew Frank,
Saman P. Amarasinghe,
Anant Agarwal:
The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs.
IEEE Micro 22(2): 25-35 (2002) |
