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Jaehwan John Lee

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2008
8 Pranav Vaidya, Jaehwan John Lee, Xiang Xiao: Multiprocessor Simulation Using Communicating Sequential Processes. MSV 2008: 215-221
7EEXiang Xiao, Jaehwan John Lee: A Novel O(1) Deadlock Detection Methodology for Multiunit Resource Systems and Its Hardware Implementation for System-on-Chip. IEEE Trans. Parallel Distrib. Syst. 19(12): 1657-1670 (2008)
2007
6 Pranav Vaidya, Jaehwan John Lee: Design Space Exploration of Multiprocessor Systems with MultiContext Reconfigurable Co-Processors. ERSA 2007: 51-60
5EEXiang Xiao, Jaehwan John Lee: A novel O(1) parallel deadlock detection algorithm and architecture for multi-unit resource systems. ICCD 2007: 480-487
4EEPranav Vaidya, Jaehwan John Lee: Simulation of hybrid computer architectures: simulators, methodologies and recommendations. VLSI-SoC 2007: 157-162
2006
3EEJaehwan John Lee, Vincent John Mooney: A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip. IEEE Trans. Parallel Distrib. Syst. 17(12): 1377-1389 (2006)
2005
2EEJaehwan John Lee, Vincent John Mooney III: A novel O(n) parallel banker's algorithm for System-on-a-Chip. ASP-DAC 2005: 1304-1308
1EEJaehwan John Lee, Vincent John Mooney III: An o(min(m, n)) parallel deadlock detection algorithm. ACM Trans. Design Autom. Electr. Syst. 10(3): 573-586 (2005)

Coauthor Index

1Vincent John Mooney III (Vincent John Mooney) [1] [2] [3]
2Pranav Vaidya [4] [6] [8]
3Xiang Xiao [5] [7] [8]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)