| 2008 |
|---|
| 8 | | Pranav Vaidya,
Jaehwan John Lee,
Xiang Xiao:
Multiprocessor Simulation Using Communicating Sequential Processes.
MSV 2008: 215-221 |
| 7 | EE | Xiang Xiao,
Jaehwan John Lee:
A Novel O(1) Deadlock Detection Methodology for Multiunit Resource Systems and Its Hardware Implementation for System-on-Chip.
IEEE Trans. Parallel Distrib. Syst. 19(12): 1657-1670 (2008) |
| 2007 |
|---|
| 6 | | Pranav Vaidya,
Jaehwan John Lee:
Design Space Exploration of Multiprocessor Systems with MultiContext Reconfigurable Co-Processors.
ERSA 2007: 51-60 |
| 5 | EE | Xiang Xiao,
Jaehwan John Lee:
A novel O(1) parallel deadlock detection algorithm and architecture for multi-unit resource systems.
ICCD 2007: 480-487 |
| 4 | EE | Pranav Vaidya,
Jaehwan John Lee:
Simulation of hybrid computer architectures: simulators, methodologies and recommendations.
VLSI-SoC 2007: 157-162 |
| 2006 |
|---|
| 3 | EE | Jaehwan John Lee,
Vincent John Mooney:
A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip.
IEEE Trans. Parallel Distrib. Syst. 17(12): 1377-1389 (2006) |
| 2005 |
|---|
| 2 | EE | Jaehwan John Lee,
Vincent John Mooney III:
A novel O(n) parallel banker's algorithm for System-on-a-Chip.
ASP-DAC 2005: 1304-1308 |
| 1 | EE | Jaehwan John Lee,
Vincent John Mooney III:
An o(min(m, n)) parallel deadlock detection algorithm.
ACM Trans. Design Autom. Electr. Syst. 10(3): 573-586 (2005) |
