| 2007 |
|---|
| 6 | EE | Mototsugu Hamada,
Takeshi Kitahara,
Naoyuki Kawabe,
Hironori Sato,
Tsuyoshi Nishikawa,
Takayoshi Shimazawa,
Takahiro Yamashita,
Hiroyuki Hara,
Yukihito Oowaki:
An automated runtime power-gating scheme.
ICCD 2007: 382-387 |
| 5 | EE | Takeshi Kitahara,
Naoyuki Kawabe,
Fumihiro Minami,
Katsuhiro Seta,
Toshiyuki Furusawa:
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
CoRR abs/0710.4762: (2007) |
| 2005 |
|---|
| 4 | EE | Takeshi Kitahara,
Naoyuki Kawabe,
Fumihiro Minami,
Katsuhiro Seta,
Toshiyuki Furusawa:
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction.
DATE 2005: 646-647 |
| 2002 |
|---|
| 3 | EE | Kimiyoshi Usami,
Naoyuki Kawabe,
Masayuki Koizumi,
Katsuhiro Seta,
Toshiyuki Furusawa:
Automated selective multi-threshold design for ultra-low standby applications.
ISLPED 2002: 202-206 |
| 2 | EE | Gang Qu,
Naoyuki Kawabe,
Kimiyoshi Usami,
Miodrag Potkonjak:
Code Coverage-Based Power Estimation Techniques for Microprocessors.
Journal of Circuits, Systems, and Computers 11(5): 557- (2002) |
| 2000 |
|---|
| 1 | EE | Gang Qu,
Naoyuki Kawabe,
Kimiyoshi Usami,
Miodrag Potkonjak:
Function-level power estimation methodology for microprocessors.
DAC 2000: 810-813 |
