| 2007 |
|---|
| 9 | EE | Yoshiyuki Kaeriyama,
Daichi Zaitsu,
Ken-ichi Suzuki,
Hiroaki Kobayashi,
Nobuyuki Ohba:
Multi-core data streaming architecture for ray tracing.
ICCD 2007: 171-178 |
| 8 | EE | Yukinori Sato,
Ken-ichi Suzuki,
Tadao Nakamura:
Power Estimation of Partitioned Register Files in a Clustered Architecture with Performance Evaluation.
IEICE Transactions 90-D(3): 627-636 (2007) |
| 2006 |
|---|
| 7 | EE | Yoshiyuki Kaeriyama,
Daichi Zaitsu,
Kazuhiko Komatsu,
Ken-ichi Suzuki,
Tadao Nakamura,
Nobuyuki Ohba:
Ray Tracing Hardware System Using Plane-Sphere Intersections.
FPL 2006: 1-6 |
| 2005 |
|---|
| 6 | | Yukinori Sato,
Ken-ichi Suzuki,
Tadao Nakamura:
An Operand Status Based Instruction Steering Scheme for Clustered Architectures.
CDES 2005: 168-174 |
| 5 | EE | Yukinori Sato,
Ken-ichi Suzuki,
Tadao Nakamura:
Cooperation of Neighboring PEs in Clustered Architectures.
SBAC-PAD 2005: 134-142 |
| 4 | EE | Takeshi Miura,
Kentaro Sano,
Ken-ichi Suzuki,
Tadao Nakamura:
A Competitive Learning Algorithm with Controlling Maximum Distortion.
JACIII 9(2): 166-174 (2005) |
| 2004 |
|---|
| 3 | EE | Kentaro Sano,
Chiaki Takagi,
Ryusuke Egawa,
Ken-ichi Suzuki,
Tadao Nakamura:
A Systolic Memory Architecture for Fast Codebook Design based on MMPDCL Algorithm.
ITCC (1) 2004: 572-578 |
| 2001 |
|---|
| 2 | | Hiroaki Kobayashi,
Ken-ichi Suzuki,
Kentaro Sano,
Yoshiyuki Kaeriyama,
Yasumasa Saida,
Nobuyuki Oba,
Tadao Nakamura:
3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis.
ICCD 2001: 462-467 |
| 1999 |
|---|
| 1 | EE | Ken-ichi Suzuki,
Nobuyuki Oba,
Shigenori Shimizu,
Hiroaki Kobayashi,
Tadao Nakamura:
Time stamp invalidation of TLB-unified cache and its performance evaluation.
Systems and Computers in Japan 30(11): 94-106 (1999) |
