| 2009 |
| 45 | EE | Albert Meixner,
Daniel J. Sorin:
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures.
IEEE Trans. Dependable Sec. Comput. 6(1): 18-31 (2009) |
| 2008 |
| 44 | EE | Bogdan F. Romanescu,
Michael E. Bauer,
Sule Ozev,
Daniel J. Sorin:
Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching.
Conf. Computing Frontiers 2008: 129-138 |
| 43 | EE | Albert Meixner,
Daniel J. Sorin:
Detouring: Translating software to circumvent hard faults in simple cores.
DSN 2008: 80-89 |
| 42 | EE | Bogdan F. Romanescu,
Daniel J. Sorin:
Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults.
PACT 2008: 43-51 |
| 41 | EE | Albert Meixner,
Michael E. Bauer,
Daniel J. Sorin:
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores.
IEEE Micro 28(1): 52-59 (2008) |
| 2007 |
| 40 | EE | Albert Meixner,
Daniel J. Sorin:
Unified microprocessor core storage.
Conf. Computing Frontiers 2007: 23-34 |
| 39 | EE | Mahmut Yilmaz,
Albert Meixner,
Sule Ozev,
Daniel J. Sorin:
Lazy Error Detection for Microprocessor Functional Units.
DFT 2007: 361-369 |
| 38 | EE | Albert Meixner,
Daniel J. Sorin:
Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures.
HPCA 2007: 145-156 |
| 37 | EE | Sule Ozev,
Daniel J. Sorin,
Mahmut Yilmaz:
Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor.
ICCD 2007: 317-324 |
| 36 | EE | Albert Meixner,
Michael E. Bauer,
Daniel J. Sorin:
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores.
MICRO 2007: 210-222 |
| 35 | EE | Albert Meixner,
Daniel J. Sorin:
Error Detection Using Dynamic Dataflow Verification.
PACT 2007: 104-118 |
| 34 | EE | Bogdan F. Romanescu,
Michael E. Bauer,
Daniel J. Sorin,
Sule Ozev:
Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation.
PACT 2007: 424 |
| 33 | EE | Anita Lungu,
Daniel J. Sorin:
Verification-Aware Microprocessor Design.
PACT 2007: 83-93 |
| 32 | EE | Jonathan R. Carter,
Sule Ozev,
Daniel J. Sorin:
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown
CoRR abs/0710.4715: (2007) |
| 31 | EE | Fred A. Bower,
Daniel J. Sorin,
Sule Ozev:
Online diagnosis of hard faults in microprocessors.
TACO 4(2): (2007) |
| 2006 |
| 30 | EE | Albert Meixner,
Daniel J. Sorin:
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures.
DSN 2006: 73-82 |
| 29 | EE | Fred A. Bower,
Derek Hower,
Mahmut Yilmaz,
Daniel J. Sorin,
Sule Ozev:
Applying architectural vulnerability Analysis to hard faults in the microprocessor.
SIGMETRICS/Performance 2006: 375-376 |
| 28 | EE | Tong Li,
Alvin R. Lebeck,
Daniel J. Sorin:
Spin Detection Hardware for Improved Management of Multithreaded Systems.
IEEE Trans. Parallel Distrib. Syst. 17(6): 508-521 (2006) |
| 27 | EE | Jaidev P. Patwardhan,
Chris Dwyer,
Alvin R. Lebeck,
Daniel J. Sorin:
NANA: A nano-scale active network architecture.
JETC 2(1): 1-30 (2006) |
| 2005 |
| 26 | EE | Jonathan R. Carter,
Sule Ozev,
Daniel J. Sorin:
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown.
DATE 2005: 300-305 |
| 25 | EE | Albert Meixner,
Daniel J. Sorin:
Dynamic Verification of Sequential Consistency.
ISCA 2005: 482-493 |
| 24 | EE | Fred A. Bower,
Daniel J. Sorin,
Sule Ozev:
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors.
MICRO 2005: 197-208 |
| 23 | EE | Tong Li,
Carla Schlatter Ellis,
Alvin R. Lebeck,
Daniel J. Sorin:
Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution.
USENIX Annual Technical Conference, General Track 2005: 31-44 |
| 22 | EE | Chris Dwyer,
Alvin R. Lebeck,
Daniel J. Sorin:
Self-Assembled Architectures and the Temporal Aspects of Computing.
IEEE Computer 38(1): 56-64 (2005) |
| 21 | EE | Fred A. Bower,
Sule Ozev,
Daniel J. Sorin:
Autonomic Microprocessor Execution via Self-Repairing Arrays.
IEEE Trans. Dependable Sec. Comput. 2(4): 297-310 (2005) |
| 20 | EE | Milo M. K. Martin,
Daniel J. Sorin,
Bradford M. Beckmann,
Michael R. Marty,
Min Xu,
Alaa R. Alameldeen,
Kevin E. Moore,
Mark D. Hill,
David A. Wood:
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset.
SIGARCH Computer Architecture News 33(4): 92-99 (2005) |
| 2004 |
| 19 | EE | Fred A. Bower,
Paul G. Shealy,
Sule Ozev,
Daniel J. Sorin:
Tolerating Hard Faults in Microprocessor Array Structures.
DSN 2004: 51-60 |
| 18 | EE | Daniel J. Sorin,
Milo M. K. Martin,
Mark D. Hill,
David A. Wood:
Using Speculation to Simplify Multiprocessor Design.
IPDPS 2004 |
| 17 | EE | Jaidev P. Patwardhan,
Alvin R. Lebeck,
Daniel J. Sorin:
Communication breakdown: analyzing CPU usage in commercial Web workloads.
ISPASS 2004: 12-19 |
| 2003 |
| 16 | EE | Daniel J. Sorin,
Mark D. Hill,
David A. Wood:
Dynamic Verification of End-to-End Multiprocessor Invariants.
DSN 2003: 281-290 |
| 15 | EE | Milo M. K. Martin,
Pacia J. Harper,
Daniel J. Sorin,
Mark D. Hill,
David A. Wood:
Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors.
ISCA 2003: 206-217 |
| 14 | EE | Tong Li,
Alvin R. Lebeck,
Daniel J. Sorin:
Quantifying instruction criticality for shared memory multiprocessors.
SPAA 2003: 128-137 |
| 13 | EE | Alaa R. Alameldeen,
Milo M. K. Martin,
Carl J. Mauer,
Kevin E. Moore,
Min Xu,
Mark D. Hill,
David A. Wood,
Daniel J. Sorin:
Simulating a $2M Commercial Server on a $2K PC.
IEEE Computer 36(2): 50-57 (2003) |
| 12 | EE | Daniel J. Sorin,
Jonathan Lemon,
Derek L. Eager,
Mary K. Vernon:
Analytic Evaluation of Shared-Memory Architectures.
IEEE Trans. Parallel Distrib. Syst. 14(2): 166-180 (2003) |
| 2002 |
| 11 | EE | Milo M. K. Martin,
Daniel J. Sorin,
Mark D. Hill,
David A. Wood:
Bandwidth Adaptive Snooping.
HPCA 2002: 251-262 |
| 10 | EE | Daniel J. Sorin,
Milo M. K. Martin,
Mark D. Hill,
David A. Wood:
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery.
ISCA 2002: 123- |
| 9 | EE | Daniel J. Sorin,
Manoj Plakal,
Anne Condon,
Mark D. Hill,
Milo M. K. Martin,
David A. Wood:
Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol.
IEEE Trans. Parallel Distrib. Syst. 13(6): 556-578 (2002) |
| 2001 |
| 8 | EE | Milo M. K. Martin,
Daniel J. Sorin,
Harold W. Cain,
Mark D. Hill,
Mikko H. Lipasti:
Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing.
MICRO 2001: 328-337 |
| 2000 |
| 7 | EE | Milo M. K. Martin,
Daniel J. Sorin,
Anastassia Ailamaki,
Alaa R. Alameldeen,
Ross M. Dickson,
Carl J. Mauer,
Kevin E. Moore,
Manoj Plakal,
Mark D. Hill,
David A. Wood:
Timestamp snooping: an approach for extending SMPs.
ASPLOS 2000: 25-36 |
| 6 | EE | Derek L. Eager,
Daniel J. Sorin,
Mary K. Vernon:
AMVA techniques for high service time variability.
SIGMETRICS 2000: 217-228 |
| 1999 |
| 5 | EE | Anne Condon,
Mark D. Hill,
Manoj Plakal,
Daniel J. Sorin:
Using Lamport Clocks to Reason about Relaxed Memory Models.
HPCA 1999: 270-278 |
| 4 | EE | E. Ender Bilir,
Ross M. Dickson,
Ying Hu,
Manoj Plakal,
Daniel J. Sorin,
Mark D. Hill,
David A. Wood:
Multicast Snooping: A New Coherence Method Using a Multicast Address Network.
ISCA 1999: 294-304 |
| 3 | EE | Mark D. Hill,
Anne Condon,
Manoj Plakal,
Daniel J. Sorin:
A System-Level Specification Framework for I/O Architectures.
SPAA 1999: 138-147 |
| 1998 |
| 2 | EE | Daniel J. Sorin,
Vijay S. Pai,
Sarita V. Adve,
Mary K. Vernon,
David A. Wood:
Analytic Evaluation of Shared-memory Systems with ILP Processors.
ISCA 1998: 380-391 |
| 1 | EE | Manoj Plakal,
Daniel J. Sorin,
Anne Condon,
Mark D. Hill:
Lamport Clocks: Verifying a Directory Cache-Coherence Protocol.
SPAA 1998: 67-76 |