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Daniel J. Sorin

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2009
45EEAlbert Meixner, Daniel J. Sorin: Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures. IEEE Trans. Dependable Sec. Comput. 6(1): 18-31 (2009)
2008
44EEBogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin: Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching. Conf. Computing Frontiers 2008: 129-138
43EEAlbert Meixner, Daniel J. Sorin: Detouring: Translating software to circumvent hard faults in simple cores. DSN 2008: 80-89
42EEBogdan F. Romanescu, Daniel J. Sorin: Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults. PACT 2008: 43-51
41EEAlbert Meixner, Michael E. Bauer, Daniel J. Sorin: Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. IEEE Micro 28(1): 52-59 (2008)
2007
40EEAlbert Meixner, Daniel J. Sorin: Unified microprocessor core storage. Conf. Computing Frontiers 2007: 23-34
39EEMahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J. Sorin: Lazy Error Detection for Microprocessor Functional Units. DFT 2007: 361-369
38EEAlbert Meixner, Daniel J. Sorin: Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures. HPCA 2007: 145-156
37EESule Ozev, Daniel J. Sorin, Mahmut Yilmaz: Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. ICCD 2007: 317-324
36EEAlbert Meixner, Michael E. Bauer, Daniel J. Sorin: Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. MICRO 2007: 210-222
35EEAlbert Meixner, Daniel J. Sorin: Error Detection Using Dynamic Dataflow Verification. PACT 2007: 104-118
34EEBogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, Sule Ozev: Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation. PACT 2007: 424
33EEAnita Lungu, Daniel J. Sorin: Verification-Aware Microprocessor Design. PACT 2007: 83-93
32EEJonathan R. Carter, Sule Ozev, Daniel J. Sorin: Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown CoRR abs/0710.4715: (2007)
31EEFred A. Bower, Daniel J. Sorin, Sule Ozev: Online diagnosis of hard faults in microprocessors. TACO 4(2): (2007)
2006
30EEAlbert Meixner, Daniel J. Sorin: Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures. DSN 2006: 73-82
29EEFred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev: Applying architectural vulnerability Analysis to hard faults in the microprocessor. SIGMETRICS/Performance 2006: 375-376
28EETong Li, Alvin R. Lebeck, Daniel J. Sorin: Spin Detection Hardware for Improved Management of Multithreaded Systems. IEEE Trans. Parallel Distrib. Syst. 17(6): 508-521 (2006)
27EEJaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin: NANA: A nano-scale active network architecture. JETC 2(1): 1-30 (2006)
2005
26EEJonathan R. Carter, Sule Ozev, Daniel J. Sorin: Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown. DATE 2005: 300-305
25EEAlbert Meixner, Daniel J. Sorin: Dynamic Verification of Sequential Consistency. ISCA 2005: 482-493
24EEFred A. Bower, Daniel J. Sorin, Sule Ozev: A Mechanism for Online Diagnosis of Hard Faults in Microprocessors. MICRO 2005: 197-208
23EETong Li, Carla Schlatter Ellis, Alvin R. Lebeck, Daniel J. Sorin: Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution. USENIX Annual Technical Conference, General Track 2005: 31-44
22EEChris Dwyer, Alvin R. Lebeck, Daniel J. Sorin: Self-Assembled Architectures and the Temporal Aspects of Computing. IEEE Computer 38(1): 56-64 (2005)
21EEFred A. Bower, Sule Ozev, Daniel J. Sorin: Autonomic Microprocessor Execution via Self-Repairing Arrays. IEEE Trans. Dependable Sec. Comput. 2(4): 297-310 (2005)
20EEMilo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, David A. Wood: Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. SIGARCH Computer Architecture News 33(4): 92-99 (2005)
2004
19EEFred A. Bower, Paul G. Shealy, Sule Ozev, Daniel J. Sorin: Tolerating Hard Faults in Microprocessor Array Structures. DSN 2004: 51-60
18EEDaniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood: Using Speculation to Simplify Multiprocessor Design. IPDPS 2004
17EEJaidev P. Patwardhan, Alvin R. Lebeck, Daniel J. Sorin: Communication breakdown: analyzing CPU usage in commercial Web workloads. ISPASS 2004: 12-19
2003
16EEDaniel J. Sorin, Mark D. Hill, David A. Wood: Dynamic Verification of End-to-End Multiprocessor Invariants. DSN 2003: 281-290
15EEMilo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, David A. Wood: Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. ISCA 2003: 206-217
14EETong Li, Alvin R. Lebeck, Daniel J. Sorin: Quantifying instruction criticality for shared memory multiprocessors. SPAA 2003: 128-137
13EEAlaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Mark D. Hill, David A. Wood, Daniel J. Sorin: Simulating a $2M Commercial Server on a $2K PC. IEEE Computer 36(2): 50-57 (2003)
12EEDaniel J. Sorin, Jonathan Lemon, Derek L. Eager, Mary K. Vernon: Analytic Evaluation of Shared-Memory Architectures. IEEE Trans. Parallel Distrib. Syst. 14(2): 166-180 (2003)
2002
11EEMilo M. K. Martin, Daniel J. Sorin, Mark D. Hill, David A. Wood: Bandwidth Adaptive Snooping. HPCA 2002: 251-262
10EEDaniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood: SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. ISCA 2002: 123-
9EEDaniel J. Sorin, Manoj Plakal, Anne Condon, Mark D. Hill, Milo M. K. Martin, David A. Wood: Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol. IEEE Trans. Parallel Distrib. Syst. 13(6): 556-578 (2002)
2001
8EEMilo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, Mikko H. Lipasti: Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. MICRO 2001: 328-337
2000
7EEMilo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, David A. Wood: Timestamp snooping: an approach for extending SMPs. ASPLOS 2000: 25-36
6EEDerek L. Eager, Daniel J. Sorin, Mary K. Vernon: AMVA techniques for high service time variability. SIGMETRICS 2000: 217-228
1999
5EEAnne Condon, Mark D. Hill, Manoj Plakal, Daniel J. Sorin: Using Lamport Clocks to Reason about Relaxed Memory Models. HPCA 1999: 270-278
4EEE. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, David A. Wood: Multicast Snooping: A New Coherence Method Using a Multicast Address Network. ISCA 1999: 294-304
3EEMark D. Hill, Anne Condon, Manoj Plakal, Daniel J. Sorin: A System-Level Specification Framework for I/O Architectures. SPAA 1999: 138-147
1998
2EEDaniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, David A. Wood: Analytic Evaluation of Shared-memory Systems with ILP Processors. ISCA 1998: 380-391
1EEManoj Plakal, Daniel J. Sorin, Anne Condon, Mark D. Hill: Lamport Clocks: Verifying a Directory Cache-Coherence Protocol. SPAA 1998: 67-76

Coauthor Index

1Sarita V. Adve [2]
2Anastasia Ailamaki (Anastassia Ailamaki, Ailamaki Natassa) [7]
3Alaa R. Alameldeen [7] [13] [20]
4Michael E. Bauer [34] [36] [41] [44]
5Bradford M. Beckmann [20]
6E. Ender Bilir [4]
7Fred A. Bower [19] [21] [24] [29] [31]
8Harold W. Cain [8]
9Jonathan R. Carter [26] [32]
10Anne Condon [1] [3] [5] [9]
11Ross M. Dickson [4] [7]
12Chris Dwyer [22] [27]
13Derek L. Eager [6] [12]
14Carla Schlatter Ellis [23]
15Pacia J. Harper [15]
16Mark D. Hill [1] [3] [4] [5] [7] [8] [9] [10] [11] [13] [15] [16] [18] [20]
17Derek Hower [29]
18Ying Hu [4]
19Alvin R. Lebeck [14] [17] [22] [23] [27] [28]
20Jonathan Lemon [12]
21Tong Li [14] [23] [28]
22Mikko H. Lipasti [8]
23Anita Lungu [33]
24Milo M. K. Martin [7] [8] [9] [10] [11] [13] [15] [18] [20]
25Michael R. Marty [20]
26Carl J. Mauer [7] [13]
27Albert Meixner [25] [30] [35] [36] [38] [39] [40] [41] [43] [45]
28Kevin E. Moore [7] [13] [20]
29Sule Ozev [19] [21] [24] [26] [29] [31] [32] [34] [37] [39] [44]
30Vijay S. Pai [2]
31Jaidev P. Patwardhan [17] [27]
32Manoj Plakal [1] [3] [4] [5] [7] [9]
33Bogdan F. Romanescu [34] [42] [44]
34Paul G. Shealy [19]
35Mary K. Vernon [2] [6] [12]
36David A. Wood [2] [4] [7] [9] [10] [11] [13] [15] [16] [18] [20]
37Min Xu [13] [20]
38Mahmut Yilmaz [29] [37] [39]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)