| 2008 |
|---|
| 11 | EE | James Tuck,
Wonsun Ahn,
Luis Ceze,
Josep Torrellas:
SoftSig: software-exposed hardware signatures for code analysis and optimization.
ASPLOS 2008: 145-156 |
| 2007 |
|---|
| 10 | EE | James Tuck,
Wei Liu,
Josep Torrellas:
CAP: Criticality analysis for power-efficient speculative multithreading.
ICCD 2007: 409-416 |
| 9 | EE | Luis Ceze,
James Tuck,
Pablo Montesinos,
Josep Torrellas:
BulkSC: bulk enforcement of sequential consistency.
ISCA 2007: 278-289 |
| 2006 |
|---|
| 8 | EE | Luis Ceze,
James Tuck,
Josep Torrellas,
Calin Cascaval:
Bulk Disambiguation of Speculative Threads in Multiprocessors.
ISCA 2006: 227-238 |
| 7 | EE | James Tuck,
Luis Ceze,
Josep Torrellas:
Scalable Cache Miss Handling for High Memory-Level Parallelism.
MICRO 2006: 409-422 |
| 6 | EE | Wei Liu,
James Tuck,
Luis Ceze,
Wonsun Ahn,
Karin Strauss,
Jose Renau,
Josep Torrellas:
POSH: a TLS compiler that exploits program structure.
PPOPP 2006: 158-167 |
| 5 | EE | Jose Renau,
Karin Strauss,
Luis Ceze,
Wei Liu,
Smruti R. Sarangi,
James Tuck,
Josep Torrellas:
Energy-Efficient Thread-Level Speculation.
IEEE Micro 26(1): 80-91 (2006) |
| 4 | EE | Luis Ceze,
Karin Strauss,
James Tuck,
Josep Torrellas,
Jose Renau:
CAVA: Using checkpoint-assisted value prediction to hide L2 misses.
TACO 3(2): 182-208 (2006) |
| 2005 |
|---|
| 3 | EE | Jose Renau,
James Tuck,
Wei Liu,
Luis Ceze,
Karin Strauss,
Josep Torrellas:
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation.
ICS 2005: 179-188 |
| 2 | EE | Jose Renau,
Karin Strauss,
Luis Ceze,
Wei Liu,
Smruti R. Sarangi,
James Tuck,
Josep Torrellas:
Thread-Level Speculation on a CMP can be energy efficient.
ICS 2005: 219-228 |
| 2001 |
|---|
| 1 | | Jeff Gray,
Ted Bapty,
Sandeep Neema,
James Tuck:
Handling crosscutting constraints in domain-specific modeling.
Commun. ACM 44(10): 87-93 (2001) |
