Ting Wei Chiang

List of publications from the DBLP Bibliography Server - FAQ

2007

2 EE Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen: A technique for selecting CMOS transistor orders. ICCD 2007: 438-443

1 EE Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen: An efficient gate delay model for VLSI design. ICCD 2007: 450-455

2007
2	EE	Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen: A technique for selecting CMOS transistor orders. ICCD 2007: 438-443
1	EE	Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen: An efficient gate delay model for VLSI design. ICCD 2007: 450-455

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