Josep Llosa

2008
42	EE	Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero: Power-efficient VLIW design using clustering and widening. IJES 3(3): 141-149 (2008)
2007
41	EE	Kolin Paul, Joel Porquet, Josep Llosa: Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration. DSD 2007: 317-324
40	EE	Manoj Gupta, Fermín Sánchez, Josep Llosa: Merge Logic for Clustered Multithreaded VLIW Processors. DSD 2007: 353-360
39	EE	Manoj Gupta, Fermín Sánchez, Josep Llosa: Cluster-level simultaneous multithreading for VLIW processors. ICCD 2007: 121-128
2005
38	EE	Xavier Vera, Jaume Abella, Josep Llosa, Antonio González: An accurate cost model for guiding data locality transformations. ACM Trans. Program. Lang. Syst. 27(5): 946-987 (2005)
2004
37	EE	Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero: Out-of-Order Commit Processors. HPCA 2004: 48-59
36	EE	Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero: with Wide Functional Units. SAMOS 2004: 88-97
35	EE	Xavier Vera, Nerina Bermudo, Josep Llosa, Antonio González: A fast and accurate framework to analyze and optimize cache memory behavior. ACM Trans. Program. Lang. Syst. 26(2): 263-300 (2004)
34	EE	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero: Register Constrained Modulo Scheduling. IEEE Trans. Parallel Distrib. Syst. 15(5): 417-430 (2004)
33	EE	Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero: High-performance and low-power VLIW cores for numerical computations. IJHPCN 1(4): 171-179 (2004)
32	EE	Adrián Cristal, Josep Llosa, Mateo Valero, Daniel Ortega: Future ILP processors. IJHPCN 2(1): 1-10 (2004)
31	EE	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero: Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. International Journal of Parallel Programming 32(6): 447-474 (2004)
30	EE	Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero: A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. SIGARCH Computer Architecture News 32(3): 3-10 (2004)
2003
29	EE	Xavier Vera, Jaume Abella, Antonio González, Josep Llosa: Optimizing Program Locality Through CMEs and GAs. IEEE PACT 2003: 68-78
28	EE	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero: Hierarchical Clustered Register File Organization for VLIW Processors. IPDPS 2003: 77
27	EE	Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero: Kilo-instruction Processors. ISHPC 2003: 10-25
26	EE	Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero: Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. ISHPC 2003: 113-126
25	EE	Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero: A Case for Resource-conscious Out-of-order Processors. Computer Architecture Letters 2: (2003)
2002
24	EE	Jaume Abella, Antonio González, Josep Llosa, Xavier Vera: Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms. ICPP Workshops 2002: 568-580
23	EE	Josep M. Codina, Josep Llosa, Antonio González: A comparative study of modulo scheduling techniques. ICS 2002: 97-106
22	EE	Xavier Vera, Josep Llosa, Antonio González: Near-Optimal Padding for Removing Conflict Misses. LCPC 2002: 329-343
21	EE	Josep Llosa, Stefan M. Freudenberger: Reduced code size modulo scheduling in the absence of hardware support. MICRO 2002: 99-110
2001
20	EE	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero: MIRS: Modulo Scheduling with Integrated Register Spilling. LCPC 2001: 239-253
19	EE	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero: Modulo scheduling with integrated register spilling for clustered VLIW architectures. MICRO 2001: 160-169
18	EE	David López, Josep Llosa, Mateo Valero, Eduard Ayguadé: Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. IEEE Trans. Computers 50(10): 1033-1051 (2001)
17	EE	Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt: Lifetime-Sensitive Modulo Scheduling in a Production Environment. IEEE Trans. Computers 50(3): 234-249 (2001)
2000
16	EE	Xavier Vera, Josep Llosa, Antonio González, Nerina Bermudo: A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note). Euro-Par 2000: 194-198
15	EE	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero: Two-level hierarchical register file organization for VLIW processors. MICRO 2000: 137-146
14	EE	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero: Improved spill code generation for software pipelined loops. PLDI 2000: 134-144
1999
13	EE	Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham: Distributed Modulo Scheduling. HPCA 1999: 130-134
12	EE	David López, Josep Llosa, Eduard Ayguadé, Mateo Valero: Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. ICPP 1999: 22-29
1998
11	EE	Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham: Partitioned Schedules for Clustered VLIW Architectures. IPPS/SPDP 1998: 386-391
10	EE	David López, Josep Llosa, Mateo Valero, Eduard Ayguadé: Resource Widening Versus Replication: Limits and Performance-cost Trade-off. International Conference on Supercomputing 1998: 441-448
9	EE	David López, Josep Llosa, Mateo Valero, Eduard Ayguadé: Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures. MICRO 1998: 237-246
8		Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González: Modulo Scheduling with Reduced Register Pressure. IEEE Trans. Computers 47(6): 625-638 (1998)
7		Josep Llosa, Eduard Ayguadé, Mateo Valero: Quantitative Evaluation of Register Pressure on Software Pipelined Loops. International Journal of Parallel Programming 26(2): 121-142 (1998)
1997
6		Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham: Allocating Lifetimes to Queues in Software Pipelined Architectures. Euro-Par 1997: 1066-1073
5	EE	David López, Mateo Valero, Josep Llosa, Eduard Ayguadé: Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs. International Conference on Supercomputing 1997: 12-19
1996
4	EE	Josep Llosa, Mateo Valero, Eduard Ayguadé: Heuristics for Register-Constrained Software Pipelining. MICRO 1996: 250-261
1995
3		Josep Llosa, Mateo Valero, Eduard Ayguadé: Non-Consistent Dual Register Files to Reduce Register Pressure. HPCA 1995: 22-31
2	EE	Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González: Hypernode reduction modulo scheduling. MICRO 1995: 350-360
1994
1		Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé: Using Sacks to Organize Registers in VLIW Machines. CONPAR 1994: 628-639

Coauthor Index

1	Jaume Abella	[24] [29] [38]
2	Eduard Ayguadé	[1] [2] [3] [4] [5] [7] [8] [9] [10] [12] [14] [15] [17] [18] [19] [20] [26] [28] [31] [33] [34] [36] [42]
3	Nerina Bermudo	[16] [35]
4	Josep M. Codina	[23]
5	Adrián Cristal	[25] [27] [30] [32] [37]
6	Jason Eckhardt	[17]
7	Marcio Merino Fernandes	[6] [11] [13]
8	José A. B. Fortes	[1]
9	Stefan M. Freudenberger	[21]
10	Antonio González	[2] [8] [16] [17] [22] [23] [24] [29] [35] [38]
11	Manoj Gupta	[39] [40]
12	David López	[5] [9] [10] [12] [18]
13	José F. Martínez	[25] [30]
14	Daniel Ortega	[27] [32] [37]
15	Kolin Paul	[41]
16	Miquel Pericàs	[26] [33] [36] [42]
17	Joel Porquet	[41]
18	Fermín Sánchez	[39] [40]
19	Nigel P. Topham	[6] [11] [13]
20	Mateo Valero	[1] [2] [3] [4] [5] [7] [8] [9] [10] [12] [14] [15] [17] [18] [19] [20] [25] [26] [27] [28] [30] [31] [32] [33] [34] [36] [37] [42]
21	Xavier Vera	[16] [22] [24] [29] [35] [38]
22	Javier Zalamea	[14] [15] [19] [20] [26] [28] [31] [33] [34] [36] [42]

Colors in the list of coauthors