| |
| 1999 | ||
|---|---|---|
| 2 | V. Rajesh, Rajat Moona: Processor Modeling for Hardware Software Codesign. VLSI Design 1999: 132-137 | |
| 1998 | ||
| 1 | EE | V. Rajesh, Ajai Jain: Automatic Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. VLSI Design 1998: 270-273 |
| 1 | Ajai Jain | [1] |
| 2 | Rajat Moona | [2] |