Nagu R. Dhanwada

2008
16	EE	Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer: Exploring power management in multi-core systems. ASP-DAC 2008: 708-713
2007
15	EE	Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han: Performance modeling for early analysis of multi-core systems. CODES+ISSS 2007: 209-214
2006
14	EE	Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada: Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. ISQED 2006: 775-780
13	EE	Nagu R. Dhanwada, Alex Doboli, Adrián Núñez-Aldana, Ranga Vemuri: Hierarchical constraint transformation based on genetic optimization for analog system synthesis. Integration 39(3): 267-290 (2006)
2005
12	EE	Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan: A power estimation methodology for systemC transaction level models. CODES+ISSS 2005: 142-147
11	EE	Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner: Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. ICCD 2005: 689-696
2004
10	EE	Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu: Architecting voltage islands in core-based system-on-a-chip designs. ISLPED 2004: 180-185
9	EE	Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri: A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. ACM Trans. Design Autom. Electr. Syst. 9(2): 238-271 (2004)
2003
8	EE	Shyam Ramji, Nagu R. Dhanwada: Design topology aware physical metrics for placement analysis. ACM Great Lakes Symposium on VLSI 2003: 186-191
7	EE	Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal: SEAS: a system for early analysis of SoCs. CODES+ISSS 2003: 150-155
1999
6	EE	Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri: Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis. ASP-DAC 1999: 153-156
5	EE	Alex Doboli, Adrián Núñez-Aldana, Nagu R. Dhanwada, Sree Ganesan, Ranga Vemuri: Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration. DAC 1999: 951-957
4	EE	Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri: Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis. DATE 1999: 328-
3	EE	Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri: A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis. ISCAS (6) 1999: 362-365
2		Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri: Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis. VLSI Design 1999: 589-596
1998
1	EE	Nagu R. Dhanwada, Ranga Vemuri: Constraint Allocation in Analog System Synthesis. VLSI Design 1998: 253-258

Coauthor Index

1	Emrah Acar	[15]
2	Reinaldo A. Bergamaschi	[7] [15] [16]
3	Subhrajit Bhattacharya	[7]
4	Pradip Bose	[15] [16]
5	Alper Buyuktosunoglu	[15] [16]
6	John Conner	[11]
7	John A. Darringer	[7] [15] [16]
8	Gero Dittmann	[15] [16]
9	Alex Doboli (Alexa Doboli)	[5] [9] [13]
10	William E. Dougherty	[7]
11	Sree Ganesan	[5]
12	Guoling Han	[15] [16]
13	Jingcao Hu	[10]
14	Zhigang Hu	[16]
15	Wei-Lun Hung	[11]
16	Geert Janssen	[15] [16]
17	Dorothy Kucar	[15]
18	Ing-Chao Lin	[12] [14]
19	Greg M. Link	[11]
20	Radu Marculescu	[10]
21	Indira Nair	[7] [15] [16]
22	Gi-Joon Nam	[15]
23	Vijay Narayanan	[12]
24	Adrián Núñez-Aldana	[2] [3] [4] [5] [6] [9] [13]
25	Sarala Paliwal	[7]
26	Hiren D. Patel	[15] [16]
27	Shyam Ramji	[8]
28	Youngsoo Shin	[7] [10]
29	Suresh Srinivasan	[14]
30	Ranga Vemuri	[1] [2] [3] [4] [5] [6] [9] [13]
31	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[11] [14]
32	Yuan Xie	[11]

Colors in the list of coauthors