Bharat Krishna

2003
3	EE	Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal: A novel ultra-fast heuristic for VLSI CAD steiner trees. ACM Great Lakes Symposium on VLSI 2003: 192-197
2000
2	EE	Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal: A novel technique for sea of gates global routing. ACM Great Lakes Symposium on VLSI 2000: 71-74
1998
1		Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal: Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations. VLSI Design 1998: 53-58

Coauthor Index

1	C. Y. Roger Chen	[1] [2] [3]
2	Naresh Sehgal	[1] [2] [3]