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G. N. Nandakumar

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2005
5EEG. N. Nandakumar, Nirav Patel, Raghunatha Reddy, Makeshwar Kothandaraman: Application of Douglas-Peucker Algorithm to Generate Compact but Accurate IBIS Models. VLSI Design 2005: 757-761
2004
4EENirav Patel, M. Srihari, Pooja Maheswari, G. N. Nandakumar: An Efficient Method to Generate Test Vectors for Combinational Cell Verification. VLSI Design 2004: 769-772
1998
3 Abhijit Das, Samrat Sen, Mohan Rangan, Rupesh Nayak, G. N. Nandakumar: False Path Detection at Transistor Level. VLSI Design 1998: 226-229
1993
2 Ravindranath Naiknaware, G. N. Nandakumar, Srinivasa Rao Kasa: Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation. ITC 1993: 139-148
1 Ravindranath Naiknaware, G. N. Nandakumar, Rajeev Arora, John Larkin: Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach. VLSI Design 1993: 140-143

Coauthor Index

1Rajeev Arora [1]
2Abhijit Das [3]
3Srinivasa Rao Kasa [2]
4Makeshwar Kothandaraman [5]
5John Larkin [1]
6Pooja Maheswari [4]
7Ravindranath Naiknaware [1] [2]
8Rupesh Nayak [3]
9Nirav Patel [4] [5]
10Mohan Rangan [3]
11Raghunatha Reddy [5]
12Samrat Sen [3]
13M. Srihari [4]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)