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1 | M. Bhaskar Sherigar, A. S. Mahadevan, K. Senthil Kumar, Sumam David: A Pipelined Parallel Processor to Implement MD4 Message Digest Algorithm on Xilinx FPGA. VLSI Design 1998: 394-399 |
1 | Sumam David | [1] |
2 | A. S. Mahadevan | [1] |
3 | J. Shanmugam | [2] |
4 | M. Bhaskar Sherigar | [1] |
5 | K. V. Srinivasan | [2] |