| |
| 2004 | ||
|---|---|---|
| 3 | EE | Sanjay Sengupta: Test Strategies for Nanometer Technologies. ITC 2004: 1421 |
| 2001 | ||
| 2 | EE | Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche: Test Challenges in Nanometer Technologies. J. Electronic Testing 17(3-4): 209-218 (2001) |
| 1998 | ||
| 1 | Sitaram Yadavalli, Sanjay Sengupta: Impact and Cost of Modeling Memories for ATPG for Partial Scan Designs. VLSI Design 1998: 274-278 | |
| 1 | Rajesh Galivanche | [2] |
| 2 | Sandip Kundu | [2] |
| 3 | Sitaram Yadavalli | [1] |
| 4 | Sujit T. Zachariah | [2] |