| 2008 |
|---|
| 19 | EE | Andrea Bevilacqua,
Matteo Camponeschi,
Marc Tiebout,
Andrea Gerosa,
Andrea Neviani:
Design of broadband inductorless LNAs in ultra-scaled CMOS technologies.
ISCAS 2008: 1300-1303 |
| 18 | EE | Andrea Gerosa,
Maurizio Dalla Costa,
Andrea Bevilacqua,
Daniele Vogrig,
Andrea Neviani:
An energy-detector for non-coherent impulse-radio UWB receivers.
ISCAS 2008: 2705-2708 |
| 17 | EE | Silvia Solda,
Daniele Vogrig,
Andrea Bevilacqua,
Andrea Gerosa,
Andrea Neviani:
Analog decoding of trellis coded modulation for multi-level flash memories.
ISCAS 2008: 744-747 |
| 2007 |
|---|
| 16 | EE | Andrea Bevilacqua,
Christoph Sandner,
Andrea Gerosa,
Andrea Neviani:
Quadrature VCOs Based on Coupled PLLs.
ISCAS 2007: 2140-2143 |
| 15 | EE | Andrea Gerosa,
M. Soldan,
Alessandro Bevilacqua,
Andrea Neviani:
A 0.18-µm CMOS Squarer Circuit for a Non-Coherent UWB Receiver.
ISCAS 2007: 421-424 |
| 2006 |
|---|
| 14 | EE | Alexandre Graell i Amat,
Daniele Vogrig,
Sergio Benedetto,
Guido Montorsi,
Andrea Neviani,
Andrea Gerosa:
Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code.
GLOBECOM 2006 |
| 13 | EE | Andrea Gerosa,
Andrea Bevilacqua,
Andrea Neviani,
Andrea Xotta:
An optimal architecture for a multimode ADC, based on the cascade of a Sigma Delta modulator and a flash converter.
ISCAS 2006 |
| 12 | EE | Alexandre Graell i Amat,
Sergio Benedetto,
Guido Montorsi,
Daniele Vogrig,
Andrea Neviani,
Andrea Gerosa:
Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code.
IEEE Transactions on Communications 54(11): 1973-1982 (2006) |
| 11 | EE | Alexandre Graell i Amat,
Sergio Benedetto,
Guido Montorsi,
Daniele Vogrig,
Andrea Neviani,
Andrea Gerosa:
Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code.
IEEE Transactions on Communications 54(6): 1143 (2006) |
| 2005 |
|---|
| 10 | EE | Andrea Xotta,
Andrea Gerosa,
Andrea Neviani:
A multi-mode Sigma-Delta analog-to-digital converter for GSM, UMTS and WLAN.
ISCAS (3) 2005: 2551-2554 |
| 2004 |
|---|
| 9 | | Andrea Gerosa,
Andrea Neviani:
A low-power decimation filter for a sigma-delta converter based on a power-optimized sinc filter.
ISCAS (2) 2004: 245-248 |
| 2003 |
|---|
| 8 | EE | Andrea Maniero,
Andrea Gerosa,
Andrea Neviani:
Performance optimization in micro-power, low-voltage log-domain filters in pure CMOS technology.
ISCAS (1) 2003: 565-568 |
| 7 | EE | Andrea Gerosa,
Andrea Neviani:
A very low-power 8-bit Sigma-Delta converter in a 0.8µm CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8 V.
ISCAS (5) 2003: 49-52 |
| 6 | EE | Matteo Perenzoni,
Andrea Gerosa,
Andrea Neviani:
Analog CMOS implementation of Gallager's iterative decoding algorithm applied to a block turbo code.
ISCAS (5) 2003: 813-816 |
| 2002 |
|---|
| 5 | EE | Andrea Xotta,
Daniele Vogrig,
Andrea Gerosa,
Andrea Neviani,
Alexandre Graell i Amat,
Guido Montorsi,
M. Bruccoleri,
G. Betti:
An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels.
ISCAS (5) 2002: 69-72 |
| 2001 |
|---|
| 4 | EE | Andrea Gerosa,
Arianna Novo,
A. Mengalli,
Andrea Neviani:
A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker.
ISCAS (1) 2001: 296-299 |
| 3 | EE | Stefano Zanella,
Andrea Neviani,
Enrico Zanoni,
Paolo Miliozzi,
Edoardo Charbon,
Carlo Guardiani,
Luca P. Carloni,
Alberto L. Sangiovanni-Vincentelli:
Modeling of Substrate Noise Injected by Digital Libraries.
ISQED 2001: 488- |
| 2000 |
|---|
| 2 | EE | Andrea Gerosa,
Arianna Novo,
Andrea Neviani:
Low-power sensing and digitization of cardiac signals based on sigma-delta conversion (poster session).
ISLPED 2000: 216-218 |
| 1 | EE | Alessandra Nardi,
Andrea Neviani,
Carlo Guardiani:
Realistic Worst-Case Modeling by Performance Level Principal Component Analysis.
ISQED 2000: 455-460 |
