| 2006 |
|---|
| 8 | EE | Charvaka Duvvury,
Robert Steinhoff,
Gianluca Boselli,
Vijay Reddy,
Hans Kunz,
Steve Marum,
Roger Cline:
Gate oxide failures due to anomalous stress from HBM ESD testers.
Microelectronics Reliability 46(5-6): 656-665 (2006) |
| 2004 |
|---|
| 7 | EE | Jorge Salcedo-Suñer,
Charvaka Duvvury,
Roger Cline,
Alfonso Cadena-Hernandez:
Latchup in voltage tolerant circuits: a new phenomenon.
Microelectronics Reliability 44(4): 549-562 (2004) |
| 2002 |
|---|
| 6 | EE | Charvaka Duvvury:
Issues in Deep Submicron State-of-the-Art ESD Design (Tutorial Abstract).
ISQED 2002: 8 |
| 5 | EE | Craig Salling,
Jerry Hu,
Jeff Wu,
Charvaka Duvvury,
Roger Cline,
Rith Pok:
Development of substrate-pumped nMOS protection for a 0.13 mum technology.
Microelectronics Reliability 42(6): 887-899 (2002) |
| 2001 |
|---|
| 4 | EE | Charvaka Duvvury:
Issues in Deep Submicron State-of-the-Art ESD Design.
ISQED 2001: 10 |
| 2000 |
|---|
| 3 | EE | Charvaka Duvvury:
ESD: Design For IC Chip Quality and Reliability.
ISQED 2000: 251- |
| 1994 |
|---|
| 2 | EE | Carlos H. Díaz,
Sung-Mo Kang,
Charvaka Duvvury:
Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 482-493 (1994) |
| 1993 |
|---|
| 1 | | Carlos H. Díaz,
Charvaka Duvvury,
Sung-Mo Kang:
Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices.
ISCAS 1993: 1389-1392 |
