2005 |
11 | EE | Joachim Sudbrock,
Jaan Raik,
Raimund Ubar,
Wieslaw Kuzmicz,
Witold A. Pleskacz:
Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs.
DSD 2005: 79-82 |
2004 |
10 | EE | Adam Wojtasik,
Zbigniew Jaworski,
Wieslaw Kuzmicz,
Andrzej Wielgus,
Andrzej Wakanis,
Dariusz Sarna:
Fuzzy logic controller for rate-adaptive heart pacemaker.
Appl. Soft Comput. 4(3): 259-270 (2004) |
2002 |
9 | EE | Witold A. Pleskacz,
Tomasz Borejko,
Wieslaw Kuzmicz:
CMOS Standard Cells Characterization for IDDQ Testing.
DFT 2002: 390-398 |
8 | EE | André Schneider,
Karl-Heinz Diener,
Eero Ivask,
Raimund Ubar,
Elena Gramatová,
Thomas Hollstein,
Wieslaw Kuzmicz,
Zebo Peng:
Integrated Design and Test Generation Under Internet Based Environment MOSCITO.
DSD 2002: 187-195 |
7 | EE | T. Cibáková,
María Fischerová,
Elena Gramatová,
Wieslaw Kuzmicz,
Witold A. Pleskacz,
Jaan Raik,
Raimund Ubar:
Hierarchical test generation for combinational circuits with real defects coverage.
Microelectronics Reliability 42(7): 1141-1149 (2002) |
2001 |
6 | EE | Witold A. Pleskacz,
Dominik Kasprowicz,
Tomasz Oleszczak,
Wieslaw Kuzmicz:
CMOS Standard Cells Characterization for Defect Based Testing.
DFT 2001: 384- |
5 | EE | Wieslaw Kuzmicz,
Witold A. Pleskacz,
Jaan Raik,
Raimund Ubar:
Defect-Oriented Fault Simulation and Test Generation in Digital Circuits.
ISQED 2001: 365-371 |
4 | EE | Mykola Blyzniuk,
Irena Kazymyra,
Wieslaw Kuzmicz,
Witold A. Pleskacz,
Jaan Raik,
Raimund Ubar:
Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement.
Microelectronics Reliability 41(12): 2023-2040 (2001) |
2000 |
3 | EE | Wieslaw Kuzmicz:
Internet-Based Virtual Manufacturing: A Verification Tool for IC Designs.
ISQED 2000: 315-320 |
1997 |
2 | EE | Zbigniew Jaworski,
Mariusz Niewczas,
Wieslaw Kuzmicz:
Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation.
VTS 1997: 172-176 |
1986 |
1 | EE | Wieslaw Kuzmicz:
Modeling of Minority Carrier Current in Heavily Doped Regions of Bipolar Regions.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(1): 204-214 (1986) |