2005 |
41 | EE | Kendra Cooper,
João W. Cangussu,
Rong Lin,
Ganesan Sankaranarayanan,
Ragouramane Soundararadjane,
W. Eric Wong:
An Empirical Study on the Specification and Selection of Components Using Fuzzy Logic.
CBSE 2005: 155-170 |
2003 |
40 | EE | Rong Lin:
A Reconfigurable Low-Power High-Performance Matrix Multiplier Architecture with Borrow Parallel Counters.
IPDPS 2003: 182 |
39 | EE | Rong Lin,
Koji Nakano,
Stephan Olariu,
Albert Y. Zomaya:
An Efficient Parallel Prefix Sums Architecture with Domino Logic.
IEEE Trans. Parallel Distrib. Syst. 14(9): 922-931 (2003) |
2002 |
38 | EE | Rong Lin,
Martin Margala:
Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor.
ACM Great Lakes Symposium on VLSI 2002: 172-177 |
37 | EE | Rong Lin:
Bit-Matrix Decomposition and Dynamic Reconfiguration: A Unified Arithmetic Processor Architecture, Design and Test.
IPDPS 2002 |
2001 |
36 | | Rong Lin:
A run-time reconfigurable array of multipliers architecture.
IPDPS 2001: 143 |
35 | | Rong Lin:
Inner Product Processor Designs Using High-Performance, Non-Binary Logic Circuits.
ISCA PDCS 2001: 345-350 |
34 | EE | Rong Lin:
Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design.
ISQED 2001: 325-330 |
33 | EE | Rong Lin:
Reconfigurable parallel inner product processor architectures.
IEEE Trans. VLSI Syst. 9(2): 261-272 (2001) |
2000 |
32 | EE | Rong Lin:
Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme.
EUROMICRO 2000: 2456-2463 |
31 | EE | Rong Lin,
James L. Schwing:
A Non-binary Parallel Arithmetic Architecture.
IPDPS Workshops 2000: 149-154 |
30 | EE | Rong Lin:
A Reconfigurable Low-Power High-Performance Matrix Multiplier Design.
ISQED 2000: 321-328 |
29 | EE | Rong Lin,
Koji Nakano,
Stephan Olariu,
Maria Cristina Pinotti,
James L. Schwing,
Albert Y. Zomaya:
Scalable Hardware-Algorithms for Binary Prefix Sums.
IEEE Trans. Parallel Distrib. Syst. 11(8): 838-850 (2000) |
1999 |
28 | EE | Rong Lin,
Kevin E. Kerr,
André S. Botha:
A Novel Approach for CMOS Parallel Counter Design.
EUROMICRO 1999: 1112-1119 |
27 | EE | Rong Lin,
Koji Nakano,
Stephan Olariu,
Albert Y. Zomaya:
An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic.
IPPS/SPDP 1999: 273- |
26 | | Rong Lin,
Koji Nakano,
Stephan Olariu,
Maria Cristina Pinotti,
James L. Schwing,
Albert Y. Zomaya:
Scalable Hardware-Algorithms for Binary Prefix Sums.
IPPS/SPDP Workshops 1999: 634-642 |
25 | EE | Rong Lin,
Stephan Olariu,
James L. Schwing,
Biing-Feng Wang:
The Mesh with Hybrid Buses: An Efficient Parallel Architecture for Digital Geometry.
IEEE Trans. Parallel Distrib. Syst. 10(3): 266-280 (1999) |
24 | EE | Rong Lin,
Stephan Olariu:
Efficient VLSI architectures for Columnsort.
IEEE Trans. VLSI Syst. 7(1): 135-138 (1999) |
1998 |
23 | EE | Rong Lin,
Koji Nakano,
Stephan Olariu,
Maria Cristina Pinotti,
James L. Schwing,
Albert Y. Zomaya:
A Scalable VLSI Architecture for Binary Prefix Sums.
IPPS/SPDP 1998: 333-337 |
22 | EE | Rong Lin,
Stephan Olariu:
A Fast Parallel Algorithm to Recognize P4-sparse Graphs.
Discrete Applied Mathematics 81(1-3): 191-215 (1998) |
1997 |
21 | | Rong Lin:
Reconfigurable buses with shift switches for fast final additions of parallel multipliers.
PDPTA 1997: 513-521 |
1995 |
20 | EE | Rong Lin,
Stephan Olariu:
A simple array processor for binary prefix sums.
ASAP 1995: 113- |
19 | EE | Rong Lin,
Stephan Olariu:
Reconfigurable Buses with Shift Switching: Concepts and Applications.
IEEE Trans. Parallel Distrib. Syst. 6(1): 93-102 (1995) |
18 | EE | Rong Lin,
Stephan Olariu:
A Cost-optimal Erew Breadth-first Algorithm for Ordered Trees, with Applications.
Parallel Algorithms Appl. 5(3): 187-197 (1995) |
1994 |
17 | | Rong Lin:
Convolution Computation on Shift Switching Buses.
HICSS (2) 1994: 120-129 |
16 | | Dharmavani Bhagavathi,
Venkatavasu Bokka,
Himabindu Gurla,
Rong Lin,
Stephan Olariu,
James L. Schwing,
W. Shen,
Larry Wilson:
Time-Optimal Multiple Rank Computations on Meshes with Multiple Broadcasting.
ICPP (3) 1994: 35-38 |
15 | | Rong Lin,
Stephan Olariu:
An Optimal Parallel Matching Algorithm for Cographs.
J. Parallel Distrib. Comput. 22(1): 26-36 (1994) |
14 | EE | Rong Lin,
Stephan Olariu,
James L. Schwing,
Jingyuan Zhang:
An Efficient Erew Algorithm for Minimum Path Cover and Hamiltonicity on Cographs.
Parallel Algorithms Appl. 2(1-2): 99-113 (1994) |
13 | | Rong Lin,
Stephan Olariu,
James L. Schwing,
Jingyuan Zhang:
Computing on Reconfigurable Buses - A New Computational Paradigm.
Parallel Processing Letters 4: 465-476 (1994) |
1993 |
12 | | Dharmavani Bhagavathi,
Himabindu Gurla,
Stephan Olariu,
Rong Lin,
James L. Schwing,
Jingyuan Zhang:
Square Meshes Are Not Optimal For Convex Hull Computation.
ICPP 1993: 307-310 |
11 | | Rong Lin,
Stephan Olariu,
James L. Schwing,
Jingyuan Zhang:
Simulating Enhanced Meshes, with Applications.
Parallel Processing Letters 3: 59-70 (1993) |
1992 |
10 | | Rong Lin,
Stephan Olariu:
Computing the Inner Product on Reconfigurable Buses with Shift Switching.
CONPAR 1992: 181-192 |
9 | | Rong Lin:
Reconfigurable Buses with Shift Switching - VLSI RADIX Sort.
ICPP (3) 1992: 2-9 |
8 | | Rong Lin,
Stephan Olariu:
A fast cost-optimal parallel algorithm for the lowest common ancestor problem.
Parallel Computing 18(5): 511-516 (1992) |
1991 |
7 | | Rong Lin,
Stephan Olariu:
A Simple Optimal Parallel Algorithm to Solve the Lowest Common Ancestor Problem.
ICCI 1991: 455-461 |
6 | | Rong Lin,
Stephan Olariu:
A Fast Parallel Algorithm to Compute Path Functions for Cographs.
ICPP (3) 1991: 263-266 |
5 | | Rong Lin:
Fast Algorithms for Lowest Common Ancestors on a Processor Array with Reconfigurable Buses.
Inf. Process. Lett. 40(4): 223-230 (1991) |
4 | | Rong Lin,
Stephan Olariu:
An NC Recognition Algorithm for Cographs.
J. Parallel Distrib. Comput. 13(1): 76-90 (1991) |
1990 |
3 | | Rong Lin,
Stephan Olariu:
Fast Parallel Algorithms for Cographs.
FSTTCS 1990: 176-189 |
2 | EE | Rong Lin,
Stephan Olariu:
On the parallel recognition of some tree-representable graphs.
SPDP 1990: 6-13 |
1 | | Rong Lin,
Stephan Olariu:
A Fast Parallel, Algorithm to Recognize, Partitionable Graphs.
Inf. Process. Lett. 36(3): 153-157 (1990) |