2008 |
7 | EE | Chia-Chih Yen,
Ten Lin,
Hermes Lin,
Kai Yang,
Ta-Yung Liu,
Yu-Chin Hsu:
A General Failure Candidate Ranking Framework for Silicon Debug.
VTS 2008: 352-358 |
2006 |
6 | EE | Chia-Chih Yen,
Ten Lin,
Hermes Lin,
Kai Yang,
Ta-Yung Liu,
Yu-Chin Hsu:
Diagnosing Silicon Failures Based on Functional Test Patterns.
MTV 2006: 94-98 |
5 | EE | Chia-Chih Yen,
Jing-Yang Jou:
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging.
IEEE Trans. Computers 55(11): 1356-1366 (2006) |
2004 |
4 | EE | Hue-Min Lin,
Chia-Chih Yen,
Che-Hua Shih,
Jing-Yang Jou:
On compliance test of on-chip bus for SOC.
ASP-DAC 2004: 328-333 |
3 | EE | Chia-Chih Yen,
Jing-Yang Jou,
Kuang-Chien Chen:
A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation.
IEEE Design & Test of Computers 21(2): 111-120 (2004) |
2002 |
2 | | Chia-Chih Yen,
Kuang-Chien Chen,
Jing-Yang Jou:
A Practical Approach to Cycle Bound Estimation for Property Checking.
IWLS 2002: 149-154 |
2001 |
1 | EE | Chien-Nan Jimmy Liu,
Chia-Chih Yen,
Jing-Yang Jou:
Automatic Functional Vector Generation Using the Interacting FSM Model.
ISQED 2001: 372-377 |