| 2007 |
|---|
| 7 | EE | Jing Li,
Hiroshi Miyashita:
Efficient Thermal Via Planning for Placement of 3D Integrated Circuits.
ISCAS 2007: 145-148 |
| 2006 |
|---|
| 6 | EE | Jing Li,
Hiroshi Miyashita:
Post-placement Thermal Via Planning for 3D Integrated Circuit.
APCCAS 2006: 808-811 |
| 5 | EE | Jing Li,
Hiroshi Miyashita:
Thermal-Aware Placement Based on FM Partition Scheme and Force-Directed Heuristic.
IEICE Transactions 89-A(4): 989-995 (2006) |
| 2005 |
|---|
| 4 | EE | Jing Li,
Juebang Yu,
Hiroshi Miyashita:
An Incremental Placement Algorithm for Building Block Layout Design Based on the O-Tree Representation.
IEICE Transactions 88-A(12): 3398-3404 (2005) |
| 3 | EE | Yukiko Kubo,
Hiroshi Miyashita,
Yoji Kajitani,
Kazuyuki Tateishi:
Equidistance routing in high-speed VLSI layout design.
Integration 38(3): 439-449 (2005) |
| 2004 |
|---|
| 2 | EE | Yukiko Kubo,
Hiroshi Miyashita,
Yoji Kajitani,
Kazuyuki Tateishi:
Equidistance routing in high-speed VLSI layout design.
ACM Great Lakes Symposium on VLSI 2004: 220-223 |
| 1995 |
|---|
| 1 | EE | Hiroshi Miyashita:
Extending pitchmaking algorithms to layouts with multiple grid constraints.
ASP-DAC 1995 |
