Morteza Saheb Zamani

2009
37	EE	Ali Jahanian, Morteza Saheb Zamani: Improved performance and yield with chip master planning design methodology. ACM Great Lakes Symposium on VLSI 2009: 185-190
2008
36	EE	Arash Mehdizadeh, Morteza Saheb Zamani: Proposing an efficient method to estimate and reduce crosstalk after placement in VLSI circuits. AICCSA 2008: 61-68
35	EE	Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Design space exploration for a coarse grain accelerator. ASP-DAC 2008: 685-690
34	EE	Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi: Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms. ASP-DAC 2008: 83-88
33	EE	Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani: Performance Improvement of Physical Retiming with Shortcut Insertion. ISVLSI 2008: 215-220
32	EE	Arash Mehdizadeh, Morteza Saheb Zamani, H. Shafiei: An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme. ISVLSI 2008: 233-238
31	EE	Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi: FPGA-Based Circuit Model Emulation of Quantum Algorithms. ISVLSI 2008: 399-404
30	EE	Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi: Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement. ISVLSI 2008: 467-470
29	EE	Yasaman Sanaee, Mehdi Saeedi, Morteza Saheb Zamani: Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions. ISVLSI 2008: 471-474
28	EE	Hamid Fadishei, Mehdi Saeedi, Morteza Saheb Zamani: A fast IP routing lookup architecture for multi-gigabit switching routers based on reconfigurable systems. Microprocessors and Microsystems - Embedded Hardware Design 32(4): 223-233 (2008)
27	EE	Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani: An architecture framework for an adaptive extensible processor. The Journal of Supercomputing 45(3): 313-340 (2008)
2007
26	EE	Hamid Reza Kheirabadi, Morteza Saheb Zamani: An efficient net ordering algorithm for buffer insertion. ACM Great Lakes Symposium on VLSI 2007: 521-524
25	EE	Ali Jahanian, Morteza Saheb Zamani: Improved timing closure by early buffer planning in floor-placement design flow. ACM Great Lakes Symposium on VLSI 2007: 558-563
24	EE	Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi: Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis. DSD 2007: 339-346
23	EE	Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani: A novel synthesis algorithm for reversible circuits. ICCAD 2007: 65-68
22	EE	Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. ICESS 2007: 249-260
21	EE	Hamid Reza Kheirabadi, Morteza Saheb Zamani, Mehdi Saeedi: An Efficient Analytical Approach to Path-Based Buffer Insertion. ISVLSI 2007: 219-224
20	EE	Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi: On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement. ISVLSI 2007: 428-436
19	EE	Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Zamani, Hossein Pedram, Farhad Mehdipour: An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor. VLSI-SoC 2007: 151-156
18	EE	Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs. IEICE Transactions 90-D(12): 1956-1966 (2007)
17	EE	Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian: Evaluation, prediction and reduction of routing congestion. Microelectronics Journal 38(8-9): 942-958 (2007)
2006
16	EE	Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue: An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. Asia-Pacific Computer Systems Architecture Conference 2006: 219-230
15		Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki Murakami, Hamid Noori: GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. ERSA 2006: 227-230
14	EE	Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Koji Inoue, Mehdi Sedighi: Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. EUC 2006: 722-731
13	EE	Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani: A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. FPL 2006: 1-4
12	EE	Farhad Mehdipour, Morteza Saheb Zamani, H. R. Ahmadifar, Mehdi Sedighi, Kazuaki Murakami: Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. IPDPS 2006
11	EE	Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian: Prediction and reduction of routing congestion. ISPD 2006: 72-77
10	EE	Ali Jahanian, Morteza Saheb Zamani: Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits. ISVLSI 2006: 411-415
9	EE	Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi: An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. Microprocessors and Microsystems 30(1): 52-62 (2006)
2005
8	EE	Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabaei: A novel reconfigurable hardware architecture for IP address lookup. ANCS 2005: 81-90
7	EE	Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi: Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. DSD 2005: 372-378
6	EE	Arash Hariri, Reza Rastegar, Keivan Navi, Morteza Saheb Zamani, Mohammad Reza Meybodi: Cellular Learning Automata based Evolutionary Computing (CLA-EC) for Intrinsic Hardware Evolution. Evolvable Hardware 2005: 294-297
5	EE	Arash Hariri, Reza Rastegar, Morteza Saheb Zamani, Mohammad Reza Meybodi: Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA. FCCM 2005: 311-314
4		Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghian, Farhad Mehdipour: A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms. FPT 2005: 307-308
1995
3	EE	Morteza Saheb Zamani, Graham R. Hellestrand: A neural network approach to the placement problem. ASP-DAC 1995
2		Morteza Saheb Zamani, Graham R. Hellestrand: A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement and Routing of Hierarchical Designs. ISCAS 1995: 49-52
1		Morteza Saheb Zamani, Graham R. Hellestrand: A New Neural Network Approach to the Floorplanning of Hierarchical VLSI Designs. IWANN 1995: 1128-1134

Coauthor Index

1	H. R. Ahmadifar	[12]
2	Mahdi Aminian	[31]
3	Adel Dokhanchi	[33]
4	Hamid Fadishei	[8] [28]
5	Behnam Ghavami	[19]
6	Arash Hariri	[5] [6]
7	Graham R. Hellestrand	[1] [2] [3]
8	Koji Inoue	[13] [14] [16] [18] [22] [27] [35]
9	Ali Jahanian	[10] [11] [17] [25] [33] [37]
10	Hamid Reza Kheirabadi	[21] [26]
11	Farhad Mehdipour	[4] [7] [9] [12] [13] [14] [15] [16] [18] [19] [22] [27] [35]
12	Arash Mehdizadeh	[19] [32] [36]
13	Mohammad Reza Meybodi	[5] [6]
14	Minoo Mirsaeedi	[30]
15	Kazuaki Murakami	[12] [13] [14] [15] [16] [18] [22] [27] [35]
16	Keivan Navi	[6]
17	Hamid Noori	[13] [14] [15] [16] [18] [22] [27] [35]
18	Hossein Pedram	[19]
19	Reza Rastegar	[5] [6]
20	Mostafa Rezvani	[33]
21	Masoud Sabaei	[8]
22	Babak Sadeghian	[4]
23	Mehdi Saeedi	[11] [17] [20] [21] [23] [24] [28] [29] [30] [31] [34]
24	Yasaman Sanaee	[29]
25	Mehdi Sedighi	[7] [9] [12] [14] [15] [16] [20] [23] [24] [31] [34]
26	H. Shafiei	[32]
27	Ali Valizadeh	[4]

Colors in the list of coauthors