| |
| 1996 | ||
|---|---|---|
| 3 | EE | Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng: Performance driven bus buffer insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 15(4): 429-437 (1996) |
| 1995 | ||
| 2 | EE | Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin: Performance driven multiple-source bus synthesis using buffer insertion. ASP-DAC 1995 |
| 1 | EE | Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin: Optimization of power dissipation and skew sensitivity in clock buffer synthesis. ISLPD 1995: 179-184 |
| 1 | Chung-Kuan Cheng | [1] [2] [3] |
| 2 | Jae W. Chung | [1] |
| 3 | Ting-Ting Y. Lin | [1] [2] |
| 4 | Chia-Chun Tsai | [2] [3] |