2008 |
11 | EE | Shigetaka Takagi,
Retdian A. Nicodimus,
Kazuyuki Wada,
Takahide Sato,
Nobuo Fujii:
Multi-Path Analog Circuits Robust to Digital Substrate Noise.
IEICE Transactions 91-A(2): 535-541 (2008) |
10 | EE | Ippei Akita,
Kazuyuki Wada,
Yoshiaki Tadokoro:
A 0.8-V Syllabic-Companding Log Domain Filter with 78-dB Dynamic Range in 0.35-µm CMOS.
IEICE Transactions 91-C(1): 87-95 (2008) |
2007 |
9 | EE | Ippei Akita,
Kazuyuki Wada,
Yoshiaki Tadokoro:
Simplified Low-Voltage CMOS Syllabic Companding Log Domain Filter.
ISCAS 2007: 2244-2247 |
8 | EE | Ippei Akita,
Kazuyuki Wada,
Yoshiaki Tadokoro:
Synthesis Method of All Low-Voltage CMOS Instantaneous-Companding Log Domain Integrators.
IEICE Transactions 90-A(2): 339-350 (2007) |
7 | EE | Hiroto Suzuki,
Kazuyuki Wada,
Yoshiaki Tadokoro:
Band Connections for Digital Substrate Noise Reduction Using Active Cancellation Circuits.
IEICE Transactions 90-A(2): 372-379 (2007) |
2006 |
6 | EE | Ippei Akita,
Kazuyuki Wada,
Yoshiaki Tadokoro:
Low-voltage CMOS syllabic-companding log domain filter.
ISCAS 2006 |
2005 |
5 | EE | Retdian A. Nicodimus,
Shigetaka Takagi,
Kazuyuki Wada:
Active Shield Circuit for Digital Noise Suppression in Mixed-Signal Integrated Circuits.
IEICE Transactions 88-A(2): 438-443 (2005) |
4 | EE | Retdian A. Nicodimus,
Hiroto Suzuki,
Kazuyuki Wada,
Shigetaka Takagi:
Design Optimization of Active Shield Circuits for Digital Noise Suppression Based on Average Noise Evaluation.
IEICE Transactions 88-A(2): 444-450 (2005) |
2003 |
3 | EE | Kazuyuki Wada,
Yoshiaki Tadokoro:
RC polyphase filter with flat gain characteristic.
ISCAS (1) 2003: 537-540 |
2002 |
2 | EE | Kazuyuki Wada,
Yoshiaki Tadokoro:
Design of a body-effect reduced-source follower and its application to linearization technique.
ISCAS (3) 2002: 723-726 |
1995 |
1 | EE | Kazuyuki Wada,
Shigetaka Takagi,
Zdzislaw Czarnul,
Nobuo Fujii:
Design automation for integrated continuous-time filters using integrators.
ASP-DAC 1995 |