| 2008 |
|---|
| 5 | EE | Chia-Chih Yen,
Ten Lin,
Hermes Lin,
Kai Yang,
Ta-Yung Liu,
Yu-Chin Hsu:
A General Failure Candidate Ranking Framework for Silicon Debug.
VTS 2008: 352-358 |
| 2006 |
|---|
| 4 | EE | Chia-Chih Yen,
Ten Lin,
Hermes Lin,
Kai Yang,
Ta-Yung Liu,
Yu-Chin Hsu:
Diagnosing Silicon Failures Based on Functional Test Patterns.
MTV 2006: 94-98 |
| 1998 |
|---|
| 3 | EE | Alan Su,
Yu-Chin Hsu,
Ta-Yung Liu,
Mike Tien-Chien Lee:
Eliminating false loops caused by sharing in control path.
ACM Trans. Design Autom. Electr. Syst. 3(3): 487-495 (1998) |
| 1996 |
|---|
| 2 | EE | Alan Su,
Ta-Yung Liu,
Yu-Chin Hsu,
Mike Tien-Chien Lee:
Eliminating False Loops Caused by Sharing in Control Path.
ISSS 1996: 39-44 |
| 1995 |
|---|
| 1 | EE | Shih-Hsu Huang,
Ta-Yung Liu,
Yu-Chin Hsu,
Yen-Jen Oyang:
Synthesis of false loop free circuits.
ASP-DAC 1995 |
